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TCSR0—Timer Control/Status Register 0
TCSR1—Timer Control/Status Register 1
TCSR0
Bit
Initial value
Read/Write
TCSR1
Bit
Initial value
Read/Write
Compare Match Flag A
0
1
Compare Match Flag B
0
[Clearing conditions]
• When 0 is written to CMFB after reading CMFB = 1
• When the DTC is activated by a CMIB interrupt, and the DISEL bit in the DTC's MRB register is 0
1
[Setting condition]
When TCNT = TCORB
Note: * Only 0 can be written to bits 7 to 5, to clear the flags.
604
7
6
CMFB
CMFA
0
0
R/(W)*
R/(W)*
7
6
CMFB
CMFA
0
0
R/(W)*
R/(W)*
Timer Overflow Flag
0
1
[Clearing conditions]
• When 0 is written to CMFA after reading CMFA = 1
• When the DTC is activated by a CMIA interrupt, and the DISEL bit in the DTC's MRB register is 0
[Setting condition]
When TCNT = TCORA
H'FFB2
H'FFB3
5
4
OVF
ADTE
0
0
R/(W)*
R/W
5
4
OVF
—
0
1
R/(W)*
—
Output Select
0
0
1
1
0
1
Output Select
0
0
No change when compare match B occurs
1
0 is output when compare match B occurs
1
0
1 is output when compare match B occurs
1
Output is inverted when compare match B
occurs (toggle output)
A/D Trigger Enable (TCSR0 only)
0
A/D converter start requests by compare match A are disabled
1
A/D converter start requests by compare match A are enabled
[Clearing condition]
When 0 is written to OVF after reading OVF = 1
[Setting condition]
When TCNT overflows (from H'FF to H'00)
8-Bit Timer Channel 0
8-Bit Timer Channel 1
3
2
OS3
OS2
OS1
0
0
R/W
R/W
R/W
3
2
OS3
OS2
OS1
0
0
R/W
R/W
R/W
No change when compare match A occurs
0 is output when compare match A occurs
1 is output when compare match A occurs
Output is inverted when compare match A
occurs (toggle output)
1
0
OS0
0
0
R/W
1
0
OS0
0
0
R/W
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