Dram Access Control Register (Draccr) - Hitachi H8S/2678 Series Reference Manual

4.2.9

DRAM Access Control Register (DRACCR)

Bit 7
DRMI
Initial value 0
Read/Write R/W
DRACCR is an 8-bit readable/writable register used to set the DRAM interface bus specifications.
DRACCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—Idle Cycle Insertion (DRMI): Selects whether or not an idle cycle is inserted when a
normal access cycle follows a DRAM read cycle.
Bit 7
DRMI Description
0 Idle cycle not inserted after DRAM space access
1 Idle cycle inserted after DRAM space access
Idle cycle insertion conditions, setting of number of states, etc., comply with settings
of bits ICIS1, ICIS0, and IDLC in BCR register
Bit 6—Reserved: This is a readable/writable bit, but the write value should always be 0.
Bits 5 and 4—Precharge State Control (TPC1, TPC0): These bits select the number of states in
the RAS precharge cycle in normal access and refreshing. From 1 to 4 states can be set for the
precharge cycle.
Bit 5 Bit 4
TPC1 TPC0
0 0
1
1 0
1
Bits 3 and 2—Reserved: These are readable/writable bits, but the write value should always be 0.
Bits 1 and 0—RAS-CAS Wait Control (RCD1, RCD0): These bits select whether or not a wait
cycle is to be inserted between the RAS assert cycle and CAS assert cycle. A 1- to 4-state wait
cycle can be inserted.
112
6 5
— TPC1
0 0
R/W R/W
Description
RAS precharge cycle comprises 1 state
RAS precharge cycle comprises 2 states
RAS precharge cycle comprises 3 states
RAS precharge cycle comprises 4 states
4 3
TPC0 —
0 0
R/W R/W
2 1
— RCD1
0 0
R/W R/W
(Initial value)
(Initial value)
0
RCD0
0
R/W