Hitachi H8S/2678 Series Reference Manual page 184

Bus cycle A
T
1
ø
Address bus
CS (area A)
CS (area B)
RD
Possibility of overlap between
CS (area B) and RD
(a) Idle cycle not inserted
(ICIS1 = 0)
Figure 4.46 Relationship between Chip Select (CS) and Read (RD)
Idle Cycle in Case of DRAM Space Access after Normal Space Access: In a DRAM space
access following a normal space access, the settings of bits ICIS1, ICIS0, and IDLC are valid.
However, in the case of consecutive reads in different areas, for example, if the second read is a
full access to DRAM space, only a T
case is shown figure 4.47.
ø
Address bus
RD
Data bus
Figure 4.47 Example of DRAM Full Access after External Read
Bus cycle B
T T T T
2 3 1 2
cycle is inserted, and a T
p
External read
T
1
ø
Address bus
CS (area A)
CS (area B)
RD
DRAM space read
T T T
2 3 p
(CAST = 0)
Bus cycle A Bus cycle B
T T T T
1 2 3 i
(b) Idle cycle inserted
(ICIS1 = 1 (initial value))
cycle is not. The timing in this
i
T T T
r c1 c2
T T
1 2
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