Hitachi H8S/2678 Series Reference Manual page 112

Name
Chip select 5/row address
strobe 5
Chip select 6
Chip select 7
Upper column address
strobe
Lower column address strobe
Output enable
Wait
Bus request
Bus request acknowledge
Bus request output
Data transfer acknowledge 1
(DMAC)
Data transfer acknowledge 0
(DMAC)
Data transfer acknowledge 3
(EXDMAC)
Data transfer acknowledge 2
(EXDMAC)
Data transfer acknowledge 1
(EXDMAC)
Data transfer acknowledge 0
(EXDMAC)
Abbre-
viation I/O
CS5
Output
CS6
Output
CS7
Output
UCAS
Output
LCAS
Output
OE
Output
WAIT
Input
BREQ
Input
BACK
Output
BREQO
Output
DACK1
Output
DACK0
Output
EDACK3
Output
EDACK2
Output
EDACK1
Output
EDACK0
Output
Function
Strobe signal indicating that area 5 is
selected.
DRAM row address strobe signal when
area 5 is DRAM interface space.
Strobe signal indicating that area 6 is
selected.
Strobe signal indicating that area 7 is
selected.
16-bit DRAM interface space upper column
address strobe signal.
8-bit DRAM interface space column
address strobe signal.
16-bit DRAM interface space lower column
address strobe signal.
DRAM interface space output enable signal.
Wait request signal when accessing
external space.
Request signal for release of bus to
external device.
Acknowledge signal indicating that bus has
been released.
External bus request signal used when
internal bus master accesses external
space when external bus is released.
Data transfer acknowledge signal for single
address transfer by DMAC channel 1.
Data transfer acknowledge signal for single
address transfer by DMAC channel 0.
Data transfer acknowledge signal for single
address transfer by EXDMAC channel 3.
Data transfer acknowledge signal for single
address transfer by EXDMAC channel 2.
Data transfer acknowledge signal for single
address transfer by EXDMAC channel 1.
Data transfer acknowledge signal for single
address transfer by EXDMAC channel 0.
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