Bus Specifications - Hitachi H8S/2678 Series Reference Manual

4.3.2

Bus Specifications

The external space bus specifications consist of five elements: (1) bus width, (2) number of access
states, (3) number of program wait states, (4) read strobe timing, and (5) chip select (CS) assertion
period extension states.
The bus width and number of access states for on-chip memory and internal I/O registers are
fixed, and are not affected by the bus controller.
Bus Width: A bus width of 8 or 16 bits can be selected with ABWCR. An area for which an 8-bit
bus is selected functions as an 8-bit access space, and an area for which a 16-bit bus is selected
functions as a16-bit access space.
If all areas are designated for 8-bit access, 8-bit bus mode is set; if any area is designated for 16-bit
access, 16-bit bus mode is always set.
Number of Access States: Two or three access states can be selected with ASTCR. An area for
which 2-state access is selected functions as a 2-state access space, and an area for which 3-state
access is selected functions as a 3-state access space.
With the DRAM interface and burst ROM interface, the number of access states may be
determined without regard to ASTCR.
When 2-state access space is designated, wait insertion is disabled.
When 3-state access space is designated, it is possible to insert program waits by means of the
WTCRA and WTCRB registers, and external waits by means of of the WAIT pin.
Number of Program Wait States: When 3-state access space is designated by ASTCR, the
number of program wait states to be inserted automatically is selected with WTCRA and WTCRB.
From 0 to 7 program wait states can be selected.
Table 4.3 shows the bus specifications (bus width, access states, and program wait states) for each
basic bus interface area.
119