Hitachi H8S/2678 Series Reference Manual page 645

TSR2—Timer Status Register 2
Bit 7
TCFD
Initial value 1
Read/Write R
Count Direction Flag
0 TCNT counts down
1
Note: * Can only be written with 0, to clear the flag.
628
6 5
— TCFU
1 0
— R/(W)*
Overflow Flag
0 [Clearing condition]
When 0 is written to TCFV after reading TCFV = 1
1 [Setting condition]
When the TCNT value overflows (from H'FFFF to H'0000)
Underflow Flag
0 [Clearing condition]
When 0 is written to TCFU after reading TCFU = 1
1 [Setting condition]
When the TCNT value underflows (from H'0000 to H'FFFF)
TCNT counts up
H'FFF5
4 3
TCFV —
0 0
R/(W)* —
TGRA Input Capture/Output Compare Flag
0 [Clearing conditions]
• When DTC is activated by TGIA interrupt
register is 0
• When DMAC is activated by TGIA
interrupt and DTA bit in DMAC's
DMABCR register is 1
• When 0 is written to TGFA after reading
1
[Setting conditions]
• When TCNT = TGRA while TGRA is
functioning as output compare register
• When TCNT value is transferred to TGRA
by input capture signal while TGRA is
functioning as input capture register
TGRB Input Capture/Output Compare Flag
[Clearing conditions]
0
• When DTC is activated by TGIB interrupt
and DISEL bit in DTC's MRB register is 0
• When 0 is written to TGFB after reading
TGFB = 1
1 [Setting conditions]
• When TCNT = TGRB while TGRB is
functioning as output compare register
• When TCNT value is transferred to TGRB
by input capture signal while TGRB is
functioning as input capture register
2 1
— TGFB
0 0
— R/(W)*
and DISEL bit in DTC's MRB
TPU2
0
TGFA
0
R/(W)*