Hitachi H8S/2678 Series Reference Manual page 40

Type
Bus control
DMA controller
(DMAC)
EXDMA controller
(EXDMAC)
Pin No.
Symbol FP-144
UCAS
86
LCAS
87
WAIT
85
OE
112
(OE) 133
DREQ1,
61
DREQ0,
60
(DREQ1), 35
(DREQ0) 34
TEND1,
82
TEND0,
81
(TEND1), 40
(TEND0) 36
DACK1,
84
DACK0,
83
(DACK1), 42
(DACK0), 41
EDREQ3 to
141, 140,
EDREQ0
35, 34
ETEND3 to
2, 142, 40,
ETEND0
36
EDACK3 to
4, 3, 42, 41
EDACK0
EDRAK3 to
51, 50, 59,
EDRAK0
58
I/O Name and Function
Output Upper column address strobe: Upper
column address strobe signal for 16-bit
DRAM interface space.
Column address strobe signal for 8-bit
DRAM interface space.
Output Lower column address strobe: Lower
column address strobe signal for 16-bit
DRAM interface space.
Input Wait: Requests insertion of a wait state
in the bus cycle when accessing
external 3-state address space.
Output Output enable: Output enable signal for
DRAM interface space.
Input DMA transfer request 1, 0: These
signals request DMAC activation.
Output DMA transfer end 1, 0: These signals
indicate the end of DMAC data transfer.
DMA transfer acknowledge 1, 0:
Output DMAC single address transfer
acknowledge signals.
Input EXDMA transfer request 3 to 0: These
signals request EXDMAC activation.
Output EXDMA transfer end 3 to 0: These
signals indicate the end of EXDMAC
data transfer.
EXDMA transfer acknowledge 3 to 0:
Output EXDMAC single address transfer
acknowledge signals.
EDREQ acknowledge 3 to 0: These
Output signals notify an external device of
acceptance and start of execution of an
external request.
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