Hitachi H8S/2678 Series Reference Manual page 446

Item
WDT Overflow output
delay time
SCI Input Asynchronous t
clock
cycle Synchronous
Input clock pulse
width
Input clock rise time
Input clock fall time
Transmit data delay
time
Receive data setup
time (synchronous)
Receive data hold
time (synchronous)
A/D Trigger input setup
converter time
Condition A
Symbol Min Max
t — 50
WOVD
4 —
Scyc
6 —
t 0.4 0.6
SCKW
t — 1.5
SCKr
t — 1.5
SCKf
t — 50
TXD
t 50 —
RXS
t 50 —
RXH
t 30 —
TRGS
Condition B
Min Max Unit
— 40 ns
4 — t
cyc
6 —
0.4 0.6 t
Scyc
— 1.5 t
cyc
— 1.5
— 40 ns
40 — ns
40 — ns
30 — ns
Test
Conditions
Figure 7.36
Figure 7.37
Figure 7.38
Figure 7.39
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