Hitachi H8S/2678 Series Reference Manual page 293

Pin PF3 functions as the LWR output pin when LWROE is set to 1. When LWROE is cleared
to 0, pin PF3 is an I/O port and its function can be switched with PF3DDR.
Pins PF2 to PF0 function as bus control input/output pins (LCAS, UCAS, and WAIT) when
the appropriate bus controller settings are made. Otherwise, these pins are output ports when
the corresponding PFDDR bit is set to 1, and input ports when the bit is cleared to 0.
• Mode 7 (when bit EXPE is set to 1 in SYSCR)
Pin PF7 functions as the ø output pin when the corresponding PFDDR bit is set to 1, and as an
input port when the bit is cleared to 0.
Pin PF6 functions as the AS output pin when ASOE is set to 1. When ASOE is cleared to 0,
pin PF6 is an I/O port and its function can be switched with PF6DDR.
The input/output direction specification in PFDDR is ignored for pins PF5 and PF4, which are
automatically designated as bus control outputs ( RD and HWR).
Pin PF3 functions as the LWR output pin when LWROE is set to 1. When LWROE is cleared
to 0, pin PF3 is an I/O port and its function can be switched with PF3DDR.
Pins PF2 to PF0 function as bus control input/output pins (LCAS, UCAS, and WAIT) when
the appropriate PFCR2 settings are made. Otherwise, these pins are I/O ports, and their
functions can be switched with PFDDR.
• Mode 7 (when bit EXPE is cleared to 0 in SYSCR)
Pin PF7 functions as the ø output pin when the corresponding PFDDR bit is set to 1, and as an
input port when the bit is cleared to 0.
Pins PF6 to PF0 are I/O ports, and their functions can be switched with PFDDR.
Port F Data Register (PFDR)
Bit 7
PF7DR
Initial value 0
Read/Write R/W
PFDR is an 8-bit readable/writable register that stores output data for the port F pins (PF7 to PF0).
PFDR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in
software standby mode.
276
6 5
PF6DR PF5DR
0 0
R/W R/W
4 3
PF4DR PF3DR
0 0
R/W R/W
2 1
PF2DR PF1DR
0 0
R/W R/W
0
PF0DR
0
R/W