Hitachi H8S/2678 Series Reference Manual page 305

Port H Data Direction Register (PHDDR)
Bit 7
—
Initial value 0
Read/Write —
PHDDR is a 4-bit write-only register, the individual bits of which specify input or output for the
pins of port H. PHDDR cannot be read; if it is, an undefined value will be read.
PHDDR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in
software standby mode. The OPE bit in SBYCR is used to select whether the bus control output
pins retain their output state or become high-impedance when a transition is made to software
standby mode.
• Modes 1, 2, 4, 5, and 6
When the OE output enable bit (OEE) and OE output select bit (OES) are set to 1, pin PH3
functions as the OE output pin. Otherwise, when bit CS7E is set to 1, pin PH3 functions as a
CS output pin when the corresponding PHDDR bit is set to 1, and as an input port when the bit
is cleared to 0. When bit CS7E is cleared to 0, pin PH3 is an I/O port, and its function can be
switched with PHDDR.
When the CS output enable bits (CS6E to CS4E) are set to 1, pins PH2 to PH0 function as CS
output pins when the corresponding PHDDR bit is set to 1, and as I/O ports when the bit is
cleared to 0. When CS6E to CS4E are cleared to 0, pins PH2 to PH0 are I/O ports, and their
functions can be switched with PHDDR.
• Mode 7 (when bit EXPE is set to 1 in SYSCR)
When the OE output enable bit (OEE) and OE output select bit (OES) are set to 1, pin PH3
functions as the OE output pin. Otherwise, when bit CS7E is set to 1, pin PH3 functions as a
CS output pin when the corresponding PHDDR bit is set to 1, and as an input port when the bit
is cleared to 0. When bit CS7E is cleared to 0, pin PH3 is an I/O port, and their functions can
be switched with PHDDR.
When the CS output enable bits (CS6E to CS4E) are set to 1, pins PH2 to PH0 function as CS
output pins when the corresponding PHDDR bit is set to 1, and as input ports when the bit is
cleared to 0. When CS6E to CS4E are cleared to 0, pins PH2 to PH0 are I/O ports, and their
functions can be switched with PHDDR.
• Mode 7 (when bit EXPE is cleared to 0 in SYSCR)
Pins PH3 to PH0 are I/O ports, and their functions can be switched with PHDDR.
288
6 5
— —
0 0
— —
4 3
— PH3DDR PH2DDR PH1DDR PH0DDR
0 0
— W
2 1
0 0
W W
0
0
W