Hitachi H8S/2678 Series Reference Manual page 189

DRAM space read DRAM space write
T T T T T T T
p r c1 c2 i c1 c2
Address bus
RASn (CSn)
UCAS, LCAS
WE (HWR)
OE (RD)
Data bus
Idle cycle
Note: n = 2 to 5
Figure 4.52 Example of Timing for Idle Cycle Insertion in Case of Consecutive Read and
Write Accesses to DRAM Space in RAS Down Mode
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