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ABWCR—Bus Width Control Register
Bit
ABW7
Modes 2, 4, 6
Initial value
Read/Write
R/W
Modes 1, 5, 7
Initial value
Read/Write
R/W
ASTCR—Access State Control Register
Bit
AST7
Initial value
Read/Write
R/W
518
7
6
ABW6
ABW5
1
1
R/W
R/W
0
0
R/W
R/W
7
6
AST6
AST5
1
1
R/W
R/W
Area 7 to 0 Access State Control
0 Area n is designated as 2-state access space
Wait state insertion in area n external space accesses is disabled
1
Area n external space accesses are 3-state accesses
Wait state insertion in area n external space accesses is enabled
H'FEC0
5
4
ABW4
ABW3
1
1
R/W
R/W
0
0
R/W
R/W
Area 7 to 0 Bus Width Control
0 Area n is designated as 16-bit access space
1
Area n is designated as 8-bit access space
H'FEC1
5
4
AST4
AST3
1
1
R/W
R/W
3
2
ABW2
ABW1
1
1
R/W
R/W
0
0
R/W
R/W
3
2
AST2
AST1
1
1
R/W
R/W
Bus Controller
1
0
ABW0
1
1
R/W
0
0
R/W
(n = 15 to 0)
Bus Controller
1
0
AST0
1
1
R/W
(n = 7 to 0)
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