16-Bit, 2-State Access Space: Figures 4.11 to 4.13 show bus timings for a 16-bit, 2-state access
space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used
for odd addresses, and the lower half (D7 to D0) for even addresses.
Wait states cannot be inserted.
Read
Write
Notes: 1. n = 0 to 7
2. When RDNn = 0
Figure 4.11 Bus Timing for 16-Bit, 2-State Access Space (1)
128
ø
Address bus
CSn
AS
RD
D15 to D8
D7 to D0
HWR
LWR
D15 to D8
D7 to D0
(Even Address Byte Access)
Bus cycle
T
T
1
High
Valid
High impedance
2
Valid
Invalid