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When an ITSR setting is changed, if the selected pin level before the change is different from the
selected pin level after the change, an edge may be generated internally and IRQnF (n = 0 to 15) in
ISR may be set at an unintended timing. If the IRQn interrupt (n = 0 to 15) is enabled at this time,
the associated interrupt exception handling will be executed.
To prevent unintended interrupts, make changes to ITSR settings with IRQn interrupts (n = 0 to
15) disabled, and then clear IRQnF (n = 0 to 15).
3.3.7
Software Standby Release IRQ Enable Register (SSIER)
Bit
15
SSI15
Initial value
0
Read/Write
R/W
Bit
7
SSI7
Initial value
0
Read/Write
R/W
SSIER is a 16-bit readable/writable register that selects the IRQ pins used to recover from the
software standby state.
SSIER is initialized to H'0007 by a reset and in hardware standby mode.
An IRQ interrupt used to recover from the software standby state must not be set as a DTC
activation source.
Bits 15 to 0—Software Standby Release IRQ Setting (SSI15 to SSI0): These bits select the
IRQ pins used to recover from the software standby state.
Bit n
SSIn
Description
0
IRQn requests are not sampled in the software standby state
1
When an IRQn request occurs in the software standby state, the chip recovers from
the software standby state after the elapse of the oscillation settling time
14
13
SSI14
SSI13
0
0
R/W
R/W
6
5
SSI6
SSI5
0
0
R/W
R/W
12
11
SSI12
SSI11
0
0
R/W
R/W
4
3
SSI4
SSI3
0
0
R/W
R/W
(Initial value when n = 15 to 3)
(Initial value when n = 2 to 0)
10
9
SSI10
SSI9
0
0
R/W
R/W
2
1
SSI2
SSI1
1
1
R/W
R/W
8
SSI8
0
R/W
0
SSI0
1
R/W
65
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