Basic Timing - Hitachi H8S/2678 Series Reference Manual

4.5.6

Basic Timing

Figure 4.20 shows the basic access timing for DRAM space.
The four states of the basic timing consist of one T
output cycle) state, and the T
ø
Address bus
RASn (CSn)
UCAS, LCAS
WE (HWR)
OE (RD)
Read
Data bus
WE (HWR)
OE (RD)
Write
Data bus
Note: n = 2 to 5
Figure 4.20 DRAM Basic Access Timing (RAST = 0, CAST = 0)
When DRAM space is accessed, the RD signal is output as the OE signal for DRAM. When
connecting DRAM provided with an EDO page mode, the OE signal should be connected to the
OE pin of the DRAM. Setting the OEE bit to 1 in the DRAMCR register enables the OE signal for
DRAM space to be output from a dedicated OE pin. In this case, the OE signal for DRAM space is
and T (column address output cycle) states.
c1 c2
T
p
Row address
(precharge cycle) state, one T
p
T T
r c1
Column address
High
High
(row address
r
T
c2
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