Hitachi H8S/2678 Series Reference Manual page 620

TCR0—Timer Control Register 0
TCR1—Timer Control Register 1
7
Bit
CMIEB
0
Initial value
R/W
Read/Write
Compare Match Interrupt Enable B
0 CMFB interrupt request (CMIB) is disabled
1 CMFB interrupt request (CMIB) is enabled
6 5
CMIEA OVIE
0 0
R/W R/W
Timer Overflow Interrupt Enable
0 OVF interrupt request (OVI) is disabled
1 OVF interrupt request (OVI) is enabled
Compare Match Interrupt Enable A
0 CMFA interrupt request (CMIA) is disabled
1 CMFA interrupt request (CMIA) is enabled
H'FFB0
H'FFB1
4 3
CCLR1 CCLR0
0 0
R/W R/W
Clock Select
0 0 0 Clock input disabled
1 Internal clock: count at falling
edge of ø/8
1 0 Internal clock: count at falling
edge of ø/64
1 Internal clock: count at falling
edge of ø/8192
1 0 0 For channel 0:
Count at TCNT1 overflow signal*
For channel 1:
Count at TCNT0 compare match A
1 External clock: count at rising edge
1 0 External clock: count at falling edge
1 External clock: count at both rising
and falling edges
Note: * If the clock input of channel 0 is the
TCNT1 overflow signal and that of
channel 1 is the TCNT0 compare match
signal, no incrementing clock is
generated. Do not use this setting.
Counter Clear
0 0 Clearing is disabled
1 Clear by compare match A
1 0 Clear by compare match B
1 Clear by rising edge of external reset input
8-Bit Timer Channel 0
8-Bit Timer Channel 1
2 1
CKS2 CKS1
0 0
R/W R/W
0
CKS0
0
R/W
603