Hitachi H8S/2678 Series Reference Manual page 332

*
P6n
WDDR6: Write to P6DDR
WDR6: Write to P6DR
WPFCR2: Write to PFCR2
RPOR6: Read port 6
RDR6: Read P6DR
RPFCR2: Read PFCR2
n = 4 or 5
m = 12 or 13
Figure 5.37 Port 6 Block Diagram (c) (Pins P64 and P65)
Reset
Q
P6nDDR
WDDR6
Reset
Q
P6nDR
WDR6
Reset
Q
PFCR2
DMACS
C
WPFCR2
RPFCR2
Note: * Output enable signal
Priority order: DMACS = 0
DMAC > TMR > DR
DMACS = 1
TMR > DR
R
D
C
R
D
C
R
D
DMA controller
DMA transfer acknowledge
enable
DMA transfer acknowledge
8-bit timer module
Compare match output
enable
Compare match output
RDR6
RPOR6
Interrupt controller
ITSm
IRQm
315