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WAIT
Address bus
RASn (CSn)
UCAS, LCAS
WE (HWR)
Read
OE (RD)
Data bus
UCAS, LCAS
WE (HWR)
Write
OE (RD)
Data bus
Note: Downward arrows indicate the timing of WAIT pin sampling.
n = 2 to 5
Figure 4.25 Example of Wait State Insertion Timing (1)
T
T
p
r
Row address
High
High
(2-State Column Address Output)
By WAIT pin
By program wait
T
T
c1
w
Column address
T
T
w
c2
147
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