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HD6432675
Hitachi HD6432675 Manuals
Manuals and User Guides for Hitachi HD6432675. We have
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Hitachi HD6432675 manual available for free PDF download: Reference Manual
Hitachi HD6432675 Reference Manual (647 pages)
16-Bit Single-Chip Microcomputer
Brand:
Hitachi
| Category:
Computer Hardware
| Size: 2.04 MB
Table of Contents
Table of Contents
10
Section 1 Overview
18
Overview
18
Block Diagram
23
Pin Arrangement
24
Pin Functions in each Operating Mode
25
Pin Functions
37
Port 8
43
Product Lineup
45
Package Dimensions
45
Section 2 MCU Operating Modes
46
Overview
46
Operating Mode Selection (F-ZTAT Version)
46
Operating Mode Selection (Romless and Mask ROM Versions)
48
Register Configuration
50
Register Descriptions
50
Mode Control Register (MDCR)
50
System Control Register (SYSCR)
51
Operating Mode Descriptions
52
Mode 1 (Expanded Mode with On-Chip ROM Disabled)
52
Mode 2 (Expanded Mode with On-Chip ROM Disabled)
52
Mode 3
52
Mode 4 (Expanded Mode with On-Chip ROM Enabled)
53
Mode 5 (External ROM Activation Expanded Mode with On-Chip ROM Enabled)
53
Mode 6 (External ROM Activation Expanded Mode with On-Chip ROM Enabled)
53
Mode 7 (Single-Chip Activation Mode with On-Chip ROM Enabled)
53
Modes 8 and 9 [F-ZTAT Version Only]
54
Mode 10 [F-ZTAT Version Only]
54
Mode 11
54
Mode 12
54
Modes 13 and 14 [F-ZTAT Version Only]
54
Mode 15 [F-ZTAT Version Only]
54
Pin Functions in each Operating Mode
55
Memory Map in each Operating Mode
56
Section 3 Exception Handling and Interrupt Controller
70
Overview
70
Exception Handling Types and Priority
70
Interrupt Controller
71
Interrupt Controller Features
71
Block Diagram
72
Pin Configuration
73
Register Configuration
74
Register Descriptions
75
Interrupt Control Register (INTCR)
75
Interrupt Priority Registers a to K (IPRA to IPRK)
76
IRQ Enable Register (IER)
77
IRQ Sense Control Registers H and L (ISCRH, ISCRL)
78
IRQ Status Register (ISR)
79
IRQ Pin Select Register (ITSR)
81
Software Standby Release IRQ Enable Register (SSIER)
82
Interrupt Sources
83
External Interrupts
83
Internal Interrupts
84
Interrupt Vector Table
85
Interrupt Operation
91
Interrupt Control Modes and Interrupt Operation
91
Interrupt Control Mode 0
94
Interrupt Control Mode 2
96
Interrupt Exception Handling Sequence
98
Interrupt Response Times
100
Usage Notes
101
Contention between Interrupt Generation and Disabling
101
Instructions that Disable Interrupts
102
Periods When Interrupts Are Disabled
102
Interrupts During Execution of EEPMOV Instruction
102
DTC and DMAC Activation by Interrupt
102
Overview
102
Block Diagram
103
Operation
104
Section 4 Bus Controller
108
Overview
108
Features
108
Block Diagram
110
Pin Configuration
111
Register Configuration
113
Register Descriptions
114
Bus Width Control Register (ABWCR)
114
Access State Control Register (ASTCR)
114
Wait Control Registers a and B (WTCRA, WTCRB)
115
Read Strobe Timing Control Register (RDNCR)
116
CS Assertion Period Control Registers (CSACRH, CSACRL)
118
Area 0 Burst ROM I/F Control Register (BROMCRH) Area 1 Burst ROM I/F Control Register (BROMCRL)
120
Bus Control Register (BCR)
122
DRAM Control Register (DRAMCR)
124
DRAM Access Control Register (DRACCR)
129
Refresh Control Register (REFCR)
130
Refresh Timer Counter (RTCNT)
134
Refresh Time Control Register (RTCOR)
134
Overview of Bus Control
135
Area Division
135
Bus Specifications
136
Memory Interfaces
137
Chip Select Signals
139
Basic Bus Interface
140
Overview
140
Data Size and Data Alignment
140
Valid Strobes
141
Basic Timing
143
Wait Control
151
Read Strobe (RD) Timing
153
Extension of Chip Select (CS) Assertion Period
154
DRAM Interface
155
Overview
155
Setting DRAM Space
155
Address Multiplexing
156
Data Bus
156
Pins Used for DRAM Interface
157
Basic Timing
158
Column Address Output Cycle Control
159
Row Address Output Cycle Control
160
Precharge State Control
162
Wait Control
163
Byte Access Control
166
Burst Operation
167
Refresh Control
171
DMAC and EXDMAC Single Address Transfer Mode and DRAM Interface
176
Burst ROM Interface
179
Overview
179
Basic Timing
179
Wait Control
181
Write Access
181
Idle Cycle
182
Operation
182
Pin States in Idle Cycle
190
Write Data Buffer Function
190
Bus Release
191
Overview
191
Operation
192
Pin States in External Bus Released State
193
Transition Timing
194
Usage Notes
195
Bus Arbitration
196
Overview
196
Operation
196
Bus Transfer Timing
197
Bus Controller Operation in a Reset
198
Section 5 I/O Ports
200
Overview
200
Port 1
209
Overview
209
Register Configuration
210
Pin Functions
211
Port 2
220
Overview
220
Register Configuration
221
Pin Functions
222
Port 3
231
Overview
231
Register Configuration
232
Pin Functions
234
Port 4
237
Overview
237
Register Configuration
237
Pin Functions
238
Port 5
239
Overview
239
Register Configuration
239
Pin Functions
241
Port 6
244
Overview
244
Register Configuration
244
Port F
244
Pin Functions
246
Port 7
250
Overview
250
Register Configuration
251
Pin Functions
253
Overview
257
Register Configuration
258
Pin Functions
259
Overview
263
Register Configuration
264
Pin Functions
269
Register Configuration
272
Pin Functions
274
Pin Functions
279
Register Configuration
282
Overview
286
Register Configuration
287
Pin Functions
289
Overview
291
Overview
299
Pin Functions
307
Pin Functions
309
Port States in each Processing State
309
I/O Port Block Diagrams
314
Port 1
314
Port 2
318
Port 3
320
Port 4
324
Port 5
325
Port 6
330
Port 7
333
Port 8
336
Port a
339
5.19.10 Port B
341
5.19.11 Port C
342
5.19.12 Port D
343
5.19.13 Port E
344
5.19.14 Port F
345
5.19.15 Port G
353
5.19.16 Port H
358
Section 6 Supporting Module Block Diagrams
362
Interrupt Controller
362
Features
362
Block Diagram
362
Pins
363
DMA Controller
363
Features
363
Block Diagram
364
Pins
365
Data Transfer Controller
365
Features
365
Block Diagram
366
EXDMA Controller (EXDMAC)
367
Features
367
Block Diagram
368
Pins
369
16-Bit Timer Pulse Unit
370
Features
370
Block Diagram
371
Pins
372
Programmable Pulse Generator
373
Features
373
8-Bit Timer
375
Pins
375
Features
377
Pins
377
Block Diagram
378
Pins
378
Watchdog Timer
378
Features
379
Block Diagram
379
Serial Communication Interface
379
Pins
380
Smart Card Interface
381
Features
382
Block Diagram
383
Pins
383
Irda
383
Features
384
A/D Converter
384
Block Diagram
385
Pins
386
Features
387
Block Diagram
387
D/A Converter
387
Pins
388
Ram
389
Features
389
Block Diagrams
390
Features
390
Block Diagram
392
Electrical Characteristics of Mask ROM Version
394
Section 7 Electrical Characteristics
394
DC Characteristics
395
AC Characteristics
398
Conversion Characteristics
432
D/A Conversion Characteristics
433
Electrical Characteristics of F-ZTAT Version (H8S/2677, H8S/2676)
434
DC Characteristics
435
AC Characteristics
438
A/D Conversion Characteristics
447
D/A Conversion Characteristics
448
Flash Memory Characteristics
449
Usage Note
451
Section 8 Registers
452
List of Registers (by Module)
464
Register Descriptions
475
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