Hitachi H8S/2678 Series Reference Manual page 538

CSACRH, CSACRL—CS Assertion Period Control Registers
CSACRH
15
Bit
CSXH7
Initial value
R/W
Read/Write
CSACRL
Bit
CSXT7
Initial value
R/W
Read/Write
14
CSXH6 CSXH5
0 0
R/W R/W
CS and Address Signal Assertion Period Control 1
CSXHn
0
1
7 6
CSXT6 CSXT5
0 0
R/W R/W
CS and Address Signal Assertion Period Control 2
CSXTn
0
1
13 12
CSXH4 CSXH3
0 0
R/W R/W
In area n basic bus interface access, the CSn and
address assertion period (T
In area n basic bus interface access, the CSn and
address assertion period (T
5 4
CSXT4 CSXT3
0 0
R/W R/W
In area n basic bus interface access, the CSn and
address assertion period (T
In area n basic bus interface access, the CSn and
address assertion period (T
H'FEC8
11 10
CSXH2 CSXH1
0 0
R/W R/W
Description
) is not extended
h
) is extended
h
3 2
CSXT2 CSXT1
0 0
R/W R/W
Description
) is not extended
t
) is extended
t
Bus Controller
9 8
CSXH0
0 0
R/W
(n = 7 to 0)
1 0
CSXT0
0 0
R/W
(n = 7 to 0)
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