Hitachi H8S/2678 Series Reference Manual page 466

Module Register
EXDMAC EXDMA source address register 2
channel 2
EXDMA destination address
register 2
EXDMA transfer count register 2
EXDMA mode control register 2
EXDMA address control register 2
EXDMAC EXDMA source address register 3
channel 3
EXDMA destination address
register 3
EXDMA transfer count register 3
EXDMA mode control register 3
EXDMA address control register 3
All Module stop control register
EXDMAC
channels
Bus Bus width control register
controller
Access state control register
Wait control register A
Wait control register B
Read strobe timing control register
Chip select assertion period control CSACRH
register
Burst ROM interface control
register
Bus control register
DRAM control register
DRAM access control register
Refresh control register
Refresh timer counter
Refresh time constant register
TPU0 Timer control register 0
Timer mode register 0
Timer I/O control register 0H
Timer I/O control register 0L
Abbreviation R/W
EDSAR2 R/W
EDDAR2 R/W
EDTCR2 R/W
EDMDR2 R/W*
EDACR2 R/W
EDSAR3 R/W
EDDAR3 R/W
EDTCR3 R/W
EDMDR3 R/W*
EDACR3 R/W
MSTPCR R/W
ABWCR R/W
ASTCR R/W
WTCRA R/W
WTCRB R/W
RDNCR R/W
R/W
CSACRL R/W
BROMCRH R/W
BROMCRL R/W
BCR R/W
DRAMCR R/W
DRACCR R/W
REFCR R/W
RTCNT R/W
RTCOR R/W
TCR0 R/W
TMDR0 R/W
TIOR0H R/W
TIOR0L R/W
Initial Value Address*
Undefined H'FDE0
Undefined H'FDE4
Undefined H'FDE8
5
H'0000 H'FDEC
H'0000 H'FDEE
Undefined H'FDF0
Undefined H'FDF4
Undefined H'FDF8
5
H'0000 H'FDFC
H'0000 H'FDFE
H'0FFF H'FF40
6
H'FF/H'00* H'FEC0
H'FF H'FEC1
H'7777 H'FEC2
H'7777 H'FEC4
H'00 H'FEC6
H'00 H'FEC8
H'00 H'FEC9
H'00 H'FECA
H'00 H'FECB
H'1C00 H'FECC
H'0000 H'FED0
H'00 H'FED2
H'0000 H'FED4
H'00 H'FED6
H'FF H'FED7
H'00 H'FFD0
H'C0 H'FFD1
H'00 H'FFD2
H'00 H'FFD3
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