Hitachi H8S/2678 Series Reference Manual page 477

16-bit single-chip microcomputer

Table of Contents

MRB—DTC Mode Register B

Initial value

DTC Chain Transfer Enable

0 DTC data transfer finished (waiting for activation)

SAR—DTC Source Address Register

Initial value

*: Undefined

DTC Chain Transfer Select

DTC Interrupt Select

0 After a data transfer ends, the CPU interrupt is disabled

unless the transfer counter is 0

After a data transfer ends, the CPU interrupt is enabled

DTC chain transfer (new register information is read,

and data transfer performed)

Specifies data transfer source address

H'BC00 to H'BFFF

No chain transfer (activation-standby

state entered at end of DTC data transfer)

Chain transfer every time

Chain transfer only when transfer counter = 0

H'BC00 to H'BFFF

Reserved bits