Hitachi H8S/2678 Series Reference Manual page 629

TMDR0—Timer Mode Register 0
Bit
—
Initial value
Read/Write —
612
7 6
— BFB
1 1
— R/W
TGRB Buffer Operation
H'FFD1
5 4
BFA MD3
0 0
R/W R/W
Mode
0
1
Notes: 1. MD3 is a reserved bit.
TGRA Buffer Operation
0 TGRA operates normally
1 TGRA and TGRC used together for buffer
operation
0 TGRB operates normally
1 TGRB and TGRD used together for buffer
operation
3 2
MD2 MD1
0 0
R/W R/W
0 0 0 Normal operation
1 Reserved
1 0 PWM mode 1
1 PWM mode 2
1 0 0 Phase counting mode 1
1 Phase counting mode 2
1 0 Phase counting mode 3
1 Phase counting mode 4
—
* * *
In a write, it should always be
written with 0.
2. Phase counting mode cannot
be set for channels 0 and 3.
In this case, 0 should always
be written to MD2.
TPU0
1 0
MD0
0 0
R/W
*: Don't care