Hitachi H8S/2678 Series Reference Manual page 632

16-bit single-chip microcomputer
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TIER0—Timer Interrupt Enable Register 0
Bit
7
TTGE
Initial value
0
Read/Write
R/W
A/D Conversion Start Request Enable
0 A/D conversion start request generation disabled
1
6
5
1
0
Overflow Interrupt Enable
0 Interrupt request (TCIV) by TCFV disabled
1
Interrupt request (TCIV) by TCFV enabled
A/D conversion start request generation enabled
H'FFD4
4
3
TCIEV
TGIED
0
0
R/W
R/W
TGR Interrupt Enable B
0
1
TGR Interrupt Enable C
0
Interrupt request (TGIC)
by TGFC bit disabled
1
Interrupt request (TGIC)
by TGFC bit enabled
TGR Interrupt Enable D
0
Interrupt request (TGID)
by TGFD bit disabled
1
Interrupt request (TGID)
by TGFD bit enabled
2
1
TGIEC
TGIEB
0
0
R/W
R/W
TGR Interrupt Enable A
Interrupt request (TGIA)
0
by TGFA bit disabled
1
Interrupt request (TGIA)
by TGFA bit enabled
Interrupt request (TGIB)
by TGFB bit disabled
Interrupt request (TGIB)
by TGFB bit enabled
TPU0
0
TGIEA
0
R/W
615

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