Block Diagram - Hitachi H8S/2678 Series Reference Manual

16-bit single-chip microcomputer
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6.3.2

Block Diagram

DTC register information is located in on-chip RAM*. As the DTC and on-chip RAM (1-kbyte)
are connected by a 32-bit bus, a 32-bit read or write of DTC register information can be executed
in one state.
Note: * When the DTC is used, the RAME bit must be set to 1 in SYSCR.
Interrupt controller
Interrupt
request
Legend
MRA, MRB:
CRA, CRB:
SAR:
DAR:
DTCERA to DTCERH: DTC enable registers A to H
DTVECR:
DTC
DTC
activa-
tion
request
CPU
interrupt
request
DTC mode registers A and B
DTC transfer count registers A and B
DTC source address register
DTC destination address register
DTC vector register
Figure 6.3 Block Diagram of DTC
Internal address bus
Internal data bus
On-chip RAM
349

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