Usage Notes - Hitachi H8S/2678 Series Reference Manual

4.9.5

Usage Notes

External Bus Release Function and All-Module-Clocks-Stopped Mode: In the H8S/2678
Series, if the ACSE bit is set to 1 in the MSTPCR register, and then a SLEEP instruction is
executed with the setting for all supporting module clocks to be stopped (MSTPCR = H'FFFF) or
for operation of the 8-bit timer module alone (MSTPCR = H'FFFE), and a transition is made to the
sleep state, the all-module-clocks-stopped mode is entered in which the clock is also stopped for
the bus controller and I/O ports.
In this state, the external bus release function is halted. To use the external bus release function in
sleep mode, the ACSE bit in MSTPCR must be cleared to 0.
Conversely, if a SLEEP instruction to place the chip in all-module-clocks-stopped mode is
executed in the external bus released state, the transition to all-module-clocks-stopped mode is
deferred until after the bus is recovered.
External Bus Release Function and Software Standby: In the H8S/2678 Series, internal bus
master operation does not stop even while the bus is released, as long as the program is running in
on-chip ROM, etc., and no external access occurs. If a SLEEP instruction to place the chip in
software standby mode is executed while the external bus is released, the transition to software
standby mode is deferred until after the bus is recovered.
Also, since clock oscillation halts in software standby mode, if BREQ goes low in this mode,
indicating an external bus release request, the request cannot be answered until the chip has
recovered from the software standby state.
External Bus Release Function and CBR Refreshing: CBR refreshing cannot be executed while
the external bus is released. Setting the BREQOE bit to 1 in the BCR register beforehand enables
the BREQO signal to be output when a CBR refresh request is issued.
BREQO Output Timing: When the BREQOE bit is set to 1 and the BREQO signal is output,
BREQO may go low before the BACK signal.
This will occur if the next external access request or CBR refresh request occurs while internal bus
arbitration is in progress after the chip samples a low level of BREQ.
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