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4.4.7
Extension of Chip Select (CS) Assertion Period
Some external I/O devices require a setup time and hold time between address and CS signals and
strobe signals such as RD, HWR, and LWR. Settings can be made in the CSACR register to insert
states in which only the CS, AS, and address signals are asserted before and after a basic bus space
access cycle. Extension of the CS assertion period can be set for individual areas.
With the CS assertion extension period in write access, the data setup and hold times are less
stringent since the write data is output to the data bus.
Figure 4.19 shows an example of the timing when the CS assertion period is extended in basic bus
3-state access space.
ø
Address bus
CSn
AS
RD
Read
(when
RDNn = 0)
Data bus
HWR, LWR
Write
Data bus
Figure 4.19 Example of Timing when Chip Select Assertion Period is Extended
Both extension state T
basic bus cycle, or only one of these, can be specified for individual areas. Insertion or non-
insertion can be specified for the T
register, and for the T
T
h
inserted before the basic bus cycle and extension state T
h
state with the upper 8 bits (CSXH7 to CSXH0) in the CSACR
h
state with the lower 8 bits (CSXT7 to CSXT0).
t
Bus cycle
T
T
1
2
Write data
T
T
3
t
Read data
inserted after the
t
137
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