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5.10.2
Register Configuration
Table 5.17 shows the port A register configuration.
Table 5.17 Port A Registers
Name
Port A data direction register
Port A data register
Port A register
Port A MOS pull-up control register
Port A open-drain control register
Port function control register 1
Note: * Lower 16 bits of the address.
Port A Data Direction Register (PADDR)
Bit
7
PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR
Initial value
0
Read/Write
W
PADDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port A. PADDR cannot be read; if it is, an undefined value will be read.
PADDR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in
software standby mode. The OPE bit in SBYCR is used to select whether the address output pins
retain their output state or become high-impedance when a transition is made to software standby
mode.
• Modes 1, 2, 5, and 6
Pins PA4 to PA0 are address outputs regardless of the PADDR settings.
For pins PA7 to PA5, when the corresponding bit of A23E to A21E is set to 1, setting a
PADDR bit to 1 makes the corresponding port A pin an address output, while clearing the bit
to 0 makes the pin an input port. Clearing one of bits A23E to A21E to 0 makes the
corresponding port A pin an I/O port, and its function can be switched with PADDR.
Abbreviation
PADDR
PADR
PORTA
PAPCR
PAODR
PFCR1
6
5
0
0
W
W
R/W
Initial Value
W
H'00
R/W
H'00
R
Undefined
R/W
H'00
R/W
H'00
R/W
H'FF
4
3
0
0
W
W
Address*
H'FE29
H'FF69
H'FF59
H'FE36
H'FE3D
H'FE33
2
1
0
0
W
W
0
0
W
247
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