Hitachi H8S/2678 Series Reference Manual page 125

Bit 15
OEE Description
OE signal output disabled
0
OE pin can be used as I/O port
OE signal output enabled
1
Bit 14—RAS Assertion Timing Select (RAST): Selects whether, in DRAM access, the RAS
signal is asserted from the start of the T
Figure 4.4 shows the relationship between the RAST bit setting and the RAS assertion timing.
The setting of this bit applies to all areas designated as DRAM space.
Bit 14
RAST Description
RAS is asserted from ø falling edge in T
0
RAS is asserted from start of T
1
Address
RAST = 0 RAS
RAST = 1 RAS
UCAS, LCAS
Bit 13—Reserved: This is a readable/writable bit, but the write value should always be 0.
108
cycle (rising edge of ø) or from the falling edge of ø.
r
T
p
Row address
Figure 4.4 RAS Signal Assertion Timing
(2-State Column Address Output Cycle, Full Access)
cycle
r
cycle
r
Bus cycle
T T
r
T
c1 c2
Column address
(Initial value)
(Initial value)