Hitachi H8S/2678 Series Reference Manual page 444

DMAC and EXDMAC Timing
Table 7.17 DMAC and EXDMAC Timing
Condition A*: V
CC
V
SS
specifications), T
Condition B: V
CC
V
SS
specifications), T
* In planning stage
Item
DREQ setup time
DREQ hold time
TEND delay time
DACK delay time 1
DACK delay time 2
EDREQ setup time
EDREQ hold time
ETEND delay time
EDACK delay time 1
EDACK delay time 2
EDRAK delay time
= 2.7 V to 3.6 V, AV
= AV = 0 V, ø = 2 MHz to 20 MHz, T
SS
= –40°C to +85°C (wide-range specifications)
a
= 3.0 V to 3.6 V, AV
= AV = 0 V, ø = 2 MHz to 33 MHz, T
SS
= –40°C to +85°C (wide-range specifications)
a
Condition A
Symbol Min
t 30
DRQS
t 10
DRQH
t —
TED
t —
DACD1
t —
DACD2
t 30
EDRQS
t 10
EDRQH
t —
ETED
t —
EDACD1
t —
EDACD2
t —
EDRKD
= 2.7 V to 3.6 V, V
CC
a
= 3.0 V to 3.6 V, V
CC
a
Condition B
Max Min
— 25
— 10
20 —
20 —
20 —
— 25
— 10
20 —
20 —
20 —
20 —
= 2.7 V to AV
ref CC
= –20°C to +75°C (regular
= 3.0 V to AV
ref CC
= –20°C to +75°C (regular
Max Unit
— ns
—
18 ns
18
18
— ns
—
18 ns
18
18
18 ns
,
,
Test
Conditions
Figure7.27
Figure7.26
Figure7.24
Figure7.25
Figure7.27
Figure7.26
Figure7.24
Figure7.25
Figure7.28
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