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TCR0—Timer Control Register 0
Bit
CCLR2
Initial value
Read/Write
R/W
7
6
CCLR1
CCLR0
0
0
R/W
R/W
Input Clock Edge Select
0
1
Counter Clear
0
0
0
TCNT clearing disabled
1
TCNT cleared by TGRA compare match/input capture
1
0
TCNT cleared by TGRB compare match/input capture
1
TCNT cleared by counter clearing for another channel
performing synchronous clearing/synchronous operation
1
0
0
TCNT clearing disabled
1
TCNT cleared by TGRC compare match/input capture
1
0
TCNT cleared by TGRD compare match/input capture
1
TCNT cleared by counter clearing for another channel
performing synchronous clearing/synchronous operation
Notes: 1. Synchronous operation is selected by setting the SYNC bit
in TSYR to 1.
2. When TGRC or TGRD is used as a buffer register, TCNT is
not cleared because the buffer register setting has priority,
and compare match/input capture does not occur.
5
4
CKEG1
CKEG0
0
0
R/W
R/W
Time Prescaler
0
0
0
Internal clock: count on ø/1
1
Internal clock: count on ø/4
1
0
Internal clock: count on ø/16
1
Internal clock: count on ø/64
1
0
0
External clock: count on TCLKA pin input
1
External clock: count on TCLKB pin input
1
0
External clock: count on TCLKC pin input
1
External clock: count on TCLKD pin input
0
Count at rising edge
1
Count at falling edge
—
Count at both edges
H'FFD0
3
2
TPSC2
TPSC1
0
0
R/W
R/W
TPU0
1
0
TPSC0
0
0
R/W
*1
*2
*2
*1
611
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