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ø
Address bus
RD
RAS
UCAS, LCAS
Data bus
Figure 4.50 Example of Idle Cycle Operation after DRAM Access (1)
(Consecutive Reads in Different Areas) (IDLC = 0, RAST = 0, CAST = 0)
ø
Address bus
RD
HWR, LWR
RAS
UCAS, LCAS
Data bus
Figure 4.51 Example of Idle Cycle Operation after DRAM Access (2)
170
DRAM space read
T
T
T
p
r
c1
DRAM space read
T
T
T
p
r
c1
(Read after Write) (IDLC = 0, RAST = 0, CAST = 0)
External read
T
T
T
c2
i
1
Idle cycle
External write
T
T
T
c2
i
1
Idle cycle
DRAM space read
T
T
T
2
3
i
DRAM space read
T
T
T
2
3
c1
T
T
c1
c2
T
c2
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