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TCNT—Timer Counter
Bit
Initial value
Read/Write
R/W
RSTCSR—Reset Control/Status Register
Bit
WOVF
Initial value
Read/Write
R/(W)*
Watchdog Overflow Flag
Notes: * Can only be written with 0, to clear the flag.
The method for writing to RSTCSR is different from that for general registers to prevent
accidental overwriting. For details see section 11.2.4, Notes on Register Access, in the
H8S/2678 Series Hardware Manual.
7
6
0
0
R/W
R/W
7
6
RSTE
0
0
R/W
R/W
Reserved bit
Writes to this bit are invalid.
Reset Enable
0 Internal reset is not performed when TCNT overflows*
1
Internal reset is performed when TCNT overflows
Note: * The chip is not initialized internally, but the TCNT and
TCSR registers in the WDT are reset.
0 [Clearing condition]
When 0 is written to WOVF after reading TCSR when WOVF = 1
1
[Setting condition]
When TCNT overflows (from H'FF to H'00) in watchdog timer mode
H'FFBC (W) H'FFBD (R)
5
4
0
0
R/W
R/W
H'FFBE (W) H'FFBF (R)
5
4
—
—
0
1
—
3
2
0
0
R/W
R/W
3
2
—
—
1
1
—
—
WDT
1
0
0
0
R/W
WDT
1
0
—
—
1
1
—
—
607
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