Operating Mode Selection (Romless And Mask Rom Versions) - Hitachi H8S/2678 Series Reference Manual

16-bit single-chip microcomputer
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The CPU's architecture allows for 4 gigabytes of address space, but the H8S/2678 Series chip
actually accesses a maximum of 16 Mbytes.
Modes 1, 2, and 4 to 6 are externally expanded modes that allow access to external memory and
peripheral devices.
The externally expanded modes allow switching between 8-bit and 16-bit bus modes. After
program execution starts, an 8-bit or 16-bit address space can be set for each area, depending on
the bus controller setting. If 16-bit access is selected for any one area, 16-bit bus mode is set; if 8-
bit access is selected for all areas, 8-bit bus mode is set. Pin functions depend on the operating
mode.
Mode 7 is a single-chip activation externally expanded mode that allows access to external
memory and peripheral devices to be switched at the start of program execution.
In the single-chip activation externally expanded mode, it is possible to switch between externally
expanded mode and single-chip mode by means of the EXPE bit in the system control register
(SYSCR). Immediately after a reset, the chip starts up in single-chip mode, but after the start of
program execution, it is possible to change to externally expanded mode by setting EXPE
accordingly. Pin functions depend on the operating mode.
Modes 10 to 15 are boot modes and user program modes that allow programming and erasing of
flash memory. For details see section 18, ROM, in the H8S/2678 Series Hardware Manual.
The H8S/2678 Series F-ZTAT Version can be used only in modes 1, 2, 4 to 7, and 10 to 15. This
means that the flash write enable pin and mode pins must be set to select one of these modes.
Do not change the inputs at the mode pins during operation.
2.1.2

Operating Mode Selection (ROMless and Mask ROM Versions)

The H8S/2678 Series ROMless and mask ROM versions have six operating modes* (modes 1, 2,
and 4 to 7) that are selected by the mode pins (MD2 to MD0). The input at these pins determines
the CPU operating mode, enabling or disabling of on-chip ROM, and the initial bus width, as
shown in table 2.2.
Table 2.2 lists the MCU operating modes.
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