Hitachi H8S/2678 Series Reference Manual page 494

7
Bit
EDIE
0
Initial value
Read/Write R/(W)
EXDMA Interrupt Enable
0 Interrupt request is not generated
1 Interrupt request is generated
Note: * Bit IRF can only be written with 0 after being read as 1, to clear the flag.
6 5
IRF TCEIE
0 0
R/(W) *
R/W
Single Address Direction
0
1
Transfer Counter End Interrupt Enable
0 Transfer end interrupt requests by transfer counter are disabled
1 Transfer end interrupt requests by transfer counter are enabled
Interrupt Request Flag
0 No interrupt request source
[Clearing conditions]
• Writing 1 to the EDA bit in EDMDR
• Writing 0 to IRF after reading IRF = 1
1 Interrupt request source occurrence
[Setting conditions]
• Transfer end interrupt request generated by transfer counter
• Source address repeat area overflow interrupt request
• Destination address repeat area overflow interrupt request
4 3
SDIR DTSIZE
0 0
R/W R/W
Bus Give-Up
Data Transmit Size
0 Byte-size (8-bit) specification
1 Word-size (16-bit) specification
Transfer direction: EDSAR → external device with DACK
Transfer direction: External device with DACK → EDDAR
2 1
BGUP —
0 0
R/W R/W
0 Bus is not released in burst
mode or block transfer mode
1 In burst mode or block transfer
mode, the bus is transferred if
requested by an internal bus
master
0
—
0
R/W
477