Hitachi H8S/2678 Series Reference Manual page 174

ø
A23 to A0
CS
AS
RD
HWR (WE)
RAS
CAS
Figure 4.37 Example of CBR Refresh Timing (CBRM = 1)
Self-Refreshing: A self-refresh mode (battery backup mode) is provided for DRAM as a kind of
standby mode. In this mode, refresh timing and refresh addresses are generated within the DRAM.
To select self-refreshing, set the RFSHE bit and SLFRF bit to 1 in the REFCR register. When a
SLEEP instruction is executed to enter software standby mode, the CAS and RAS signals are
output and DRAM enters self-refresh mode, as shown in figure 4.38.
When software standby mode is exited, the SLFRF bit is cleared to 0 and self-refresh mode is
exited automatically.
If a CBR refresh request occurs when making a transition to software standby mode, CBR
refreshing is executed, then self-refresh mode is entered.
When using self-refresh mode, the OPE bit must not be cleared to 0 in the SBYCR register.
Normal access space request
Refresh period
157