5.19.2
Port 2
*
P2n
WDDR2: Write to P2DDR
WDR2:
Write to P2DR
RPOR2: Read port 2
RDR2:
Read P2DR
n = 0 to 5
m = 8 to 13
Note: * Output enable signal
Priority order: TPU > PPG > DR
Figure 5.21 Port 2 Block Diagram (a) (Pins P20 to P25)
Reset
R
Q
D
P2nDDR
C
WDDR2
Reset
R
Q
D
P2nDR
C
PPG module
WDR2
Pulse output enable
Pulse output
TPU module
Output compare output/
PWM output enable
Output compare output/
RDR2
PWM output
RPOR2
Input capture input
Interrupt controller
ITSm
IRQmB
301