Lvr Electrical Characteristics; Power-On Reset Characteristics; System Architecture; Clocking And Pipelining - Holtek BS83A04C Manual

LVR Electrical Characteristics

Symbol Parameter
V Low Voltage Reset Voltage
LVR
I Operating current
LVRBG
t Minimum Low Voltage Width to Reset
LVR

Power-on Reset Characteristics

Symbol Parameter
V V Start Voltage to Ensure Power-on Reset
POR DD
RR V Rising Rate to Ensure Power-on Reset
POR DD
Minimum Time for V
DD
t
POR
Power-on Reset

System Architecture

A key factor in the high-performance features of the Holtek range of microcontrollers is attributed
to their internal system architecture. The device takes advantage of the usual features found within
RISC microcontrollers providing increased speed of operation and Periodic performance. The
pipelining scheme is implemented in such a way that instruction fetching and instruction execution
are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch
or call instructions. An 8-bit wide ALU is used in practically all instruction set operations, which
carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions,
etc. The internal data path is simplified by moving data through the Accumulator and the ALU.
Certain internal registers are implemented in the Data Memory and can be directly or indirectly
addressed. The simple addressing methods of these registers along with additional architectural
features ensure that a minimum of external components is required to provide a functional I/O
control system with maximum reliability and flexibility. This makes the device suitable for low-cost,
high-volume production for controller applications.

Clocking and Pipelining

The main system clock, derived from either an HIRC or LIRC oscillator is subdivided into four
internally generated non-overlapping clocks, T1~T4. The Program Counter is incremented at the
beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4
clocks carry out the decoding and execution functions. In this way, one T1~T4 clock cycle forms
Rev. 1.00
4-Key Enhanced Touch I/O Flash MCU
Test Conditions
V
DD
— LVR enable, voltage is 1.7V
3V
LVR enable, V
5V
—
Test Conditions
V
DD
—
—
Stays at V to Ensure
POR
—
V
DD
t
POR
14
Min. Typ.
Conditions
-5% 1.7
— —
=1.7V
LVR
— 15
— 120 240
Min. Typ.
Conditions
— — —
— 0.035 —
— 1 —
RR
POR
V
POR
Time
BS83A04C
Ta=25°C
Max. Unit
+5% V
15
μA
25
480 μs
Ta=25°C
Max. Unit
100 mV
— V/ms
— ms
March 24, 2020