Texas Instruments TMS320VC5509 Data Manual

Texas Instruments TMS320VC5509 Data Manual

Fixed-point digital signal processor
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TMS320VC5509 Fixed-Point
Digital Signal Processor
Data Manual
Literature Number: SPRS163H
April 2001 − Revised January 2008
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

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  • Page 1 Literature Number: SPRS163H April 2001 − Revised January 2008 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
  • Page 2 This page intentionally left blank...
  • Page 3 Revision History REVISION HISTORY This revision history highlights the technical changes made to SPRS163G to generate SPRS163H. Scope: PAGE(S) ADDITIONS/CHANGES/DELETIONS Table 2−3, Signal Descriptions (Continued): − Updated/changed D[15:0] FUNCTION description from “... The data bus keepers are disabled at reset, ...” to “... The data bus keepers are enabled at reset, ...”.
  • Page 4 Revision History This page intentionally left blank SPRS163H April 2001 − Revised January 2008...
  • Page 5: Table Of Contents

    ....... . . TMS320VC5509 Device Nomenclature ..........
  • Page 6: Section Page

    Contents Section Page Electrical Specifications ..............Absolute Maximum Ratings .
  • Page 7 3−1 Block Diagram of the TMS320VC5509 ..........
  • Page 8 Figures Figure Page 5−17 External Interrupt Timings ............. 5−18 Wake-Up From IDLE Timings .
  • Page 9 3−6 TMS320VC5509 Parallel Port Signal Routing ..........
  • Page 10 Tables Table Page 5−1 Thermal Resistance Characteristics ........... . 5−2 Recommended Crystal Parameters .
  • Page 11: Tms320Vc5509 Features

    On-Chip Scan-Based Emulation Logic 2.7-V – 3.6-V I/O Supply Voltage 1.6-V Core Supply Voltage TMS320C55x and MicroStar BGA are trademarks of Texas Instruments. All trademarks are the property of their respective owners. † IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
  • Page 12: Introduction

    Introduction Introduction This section describes the main features of the TMS320VC5509, lists the pin assignments, and describes the function of each pin. This data manual also provides a detailed description section, electrical specifications, parameter measurement information, and mechanical data about the available packaging.
  • Page 13: Pin Assignments

    Introduction The TMS320C55x DSP core was created with an open architecture that allows the addition of application-specific hardware to boost performance on specific algorithms. The hardware extensions on the 5509 strike the perfect balance of fixed function performance with programmable flexibility, while achieving low-power consumption, and cost that traditionally has been difficult to find in the video-processor market.
  • Page 14: Pin Assignments For The Ghh Package

    Introduction Table 2−1. Pin Assignments for the GHH Package SIGNAL SIGNAL SIGNAL SIGNAL BALL # BALL # BALL # BALL # NAME NAME NAME NAME V SS GPIO5 DV DD GPIO4 CV DD DV DD FSR0 CV DD DV DD DV DD V SS A’[0]...
  • Page 15: 2.2.2 Pin Assignments For The Pge Package

    Introduction 2.2.2 Pin Assignments for the PGE Package The TMS320VC5509PGE 144-pin low-profile quad flatpack (LQFP) pin assignments are shown in Figure 2−2 and is used in conjunction with Table 2−2 to locate signal names and pin numbers. DV is the power supply for the I/O pins while CV is the power supply for the core CPU.
  • Page 16: Pin Assignments For The Pge Package

    Introduction Table 2−2. Pin Assignments for the PGE Package PIN NO. SIGNAL NAME PIN NO. SIGNAL NAME PIN NO. SIGNAL NAME PIN NO. SIGNAL NAME V SS V SS V SS RDV DD RCV DD RTCINX2 RTCINX1 USBV DD CV DD V SS GPIO7 CV DD...
  • Page 17: Signal Descriptions

    Introduction Signal Descriptions Table 2−3 lists each signal, function, and operating mode(s) grouped by function. See Section 2.2 for pin locations based on package type. Table 2−3. Signal Descriptions TERMINAL MULTIPLEXED RESET I/O/Z † BK ‡ FUNCTION NAME SIGNAL NAME CONDITION PARALLEL BUS A subset of the parallel address bus A13−A0 of the C55x...
  • Page 18 Introduction Table 2−3. Signal Descriptions (Continued) TERMINAL MULTIPLEXED RESET I/O/Z † BK ‡ FUNCTION NAME SIGNAL NAME CONDITION PARALLEL BUS (CONTINUED) A subset of the parallel address bus A15−A14 of the C55x DSP core bonded to external pins. These pins serve in one of two functions: EMIF address bus (EMIF.A[15:14]), or general-purpose I/O (GPIO.A[15:14]).
  • Page 19 Introduction Table 2−3. Signal Descriptions (Continued) TERMINAL MULTIPLEXED RESET I/O/Z † BK ‡ FUNCTION NAME SIGNAL NAME CONDITION PARALLEL BUS (CONTINUED) EMIF asynchronous memory read enable or general-purpose IO8. This pin serves in one of two functions: EMIF asynchronous memory read GPIO0 = 1: I/O/Z enable (EMIF.ARE) or general-purpose IO8 (GPIO8).
  • Page 20 Introduction Table 2−3. Signal Descriptions (Continued) TERMINAL MULTIPLEXED RESET I/O/Z † BK ‡ FUNCTION NAME SIGNAL NAME CONDITION PARALLEL BUS (CONTINUED) EMIF chip select for memory space CE0 or general-purpose IO9. This pin serves in one of two functions: EMIF chip select for memory space CE0 GPIO0 = 1: I/O/Z (EMIF.CE0) or general-purpose IO9 (GPIO9).
  • Page 21 Introduction Table 2−3. Signal Descriptions (Continued) TERMINAL MULTIPLEXED RESET I/O/Z † BK ‡ FUNCTION NAME SIGNAL NAME CONDITION PARALLEL BUS (CONTINUED) EMIF byte enable 0 control or HPI byte identification. This pin serves in one of two functions: EMIF byte enable 0 control (EMIF.BE0) or HPI byte I/O/Z identification (HPI.HBE0).
  • Page 22 Introduction Table 2−3. Signal Descriptions (Continued) TERMINAL MULTIPLEXED RESET I/O/Z † BK ‡ FUNCTION NAME SIGNAL NAME CONDITION PARALLEL BUS (CONTINUED) EMIF SDRAM row strobe, HPI address strobe, or general-purpose IO12. This pin serves in one of three functions: EMIF SDRAM row strobe I/O/Z (EMIF.SDRAS), HPI address strobe (HPI.HAS), or general-purpose IO12 (GPIO12).
  • Page 23 Introduction Table 2−3. Signal Descriptions (Continued) TERMINAL MULTIPLEXED RESET I/O/Z † BK ‡ FUNCTION NAME SIGNAL NAME CONDITION PARALLEL BUS (CONTINUED) SDRAM A10 address line or general-purpose IO13. This pin serves in one of two functions: SDRAM A10 address line (EMIF.SDA10) or I/O/Z general-purpose IO13 (GPIO13).
  • Page 24 Introduction Table 2−3. Signal Descriptions (Continued) TERMINAL MULTIPLEXED RESET I/O/Z † BK ‡ FUNCTION NAME SIGNAL NAME CONDITION BIT I/O SIGNALS 7-bit (LQFP package) or 8-bit (BGA package) Input/Output lines that can be individually configured as inputs or outputs, and also individually set or GPIO[7:6,4:0] (LQFP) I/O/Z reset when configured as outputs.
  • Page 25 Introduction Table 2−3. Signal Descriptions (Continued) TERMINAL MULTIPLEXED RESET I/O/Z † BK ‡ FUNCTION NAME SIGNAL NAME CONDITION MULTICHANNEL BUFFERED SERIAL PORTS SIGNALS McBSP0 receive clock. CLKR0 serves as the serial shift clock for the serial CLKR0 I/O/Z Hi-Z port receiver. At reset, this pin is in high-impedance mode. McBSP0 receive data Input McBSP0 receive frame synchronization.
  • Page 26 Introduction Table 2−3. Signal Descriptions (Continued) TERMINAL MULTIPLEXED RESET I/O/Z † BK ‡ FUNCTION NAME SIGNAL NAME CONDITION MULTICHANNEL BUFFERED SERIAL PORTS SIGNALS (CONTINUED) McBSP1 transmit clock or MultiMedia Card/Secure Digital1 data0. At I/O/Z reset, this pin is configured as McBSP1.CLKX. McBSP1 transmit clock.
  • Page 27 Introduction Table 2−3. Signal Descriptions (Continued) TERMINAL MULTIPLEXED RESET I/O/Z † BK ‡ FUNCTION NAME SIGNAL NAME CONDITION MULTICHANNEL BUFFERED SERIAL PORTS SIGNALS (CONTINUED) McBSP2 data transmit or MultiMedia Card/Secure Digital2 serial clock. At reset, this pin is configured as McBSP2.DX. McBSP2 serial data transmit.
  • Page 28 Introduction Table 2−3. Signal Descriptions (Continued) TERMINAL MULTIPLEXED RESET I/O/Z † BK ‡ FUNCTION NAME SIGNAL NAME CONDITION TEST/EMULATION PINS IEEE standard 1149.1 test clock. TCK is normally a free-running clock signal with a 50% duty cycle. The changes on test access port (TAP) of input signals TMS and TDI are clocked into the TAP controller, instruction Input register, or selected test data register on the rising edge of TCK.
  • Page 29 Introduction Table 2−3. Signal Descriptions (Continued) TERMINAL MULTIPLEXED RESET I/O/Z † BK ‡ FUNCTION NAME SIGNAL NAME CONDITION SUPPLY PINS CV DD Digital Power, + V DD . Dedicated power supply for the core CPU. RV DD Digital Power, + V DD . Dedicated power supply for on-chip memory. DV DD Digital Power, + V DD .
  • Page 30: Functional Overview

    The following functional overview is based on the block diagram in Figure 3−1. USB PLL † † † † Number of pins determined by package type. Figure 3−1. Block Diagram of the TMS320VC5509 SPRS163H April 2001 − Revised January 2008...
  • Page 31: Memory

    Functional Overview Memory The 5509 supports a unified memory map (program and data accesses are made to the same physical space). The total on-chip memory is 320K bytes (128K 16-bit words of RAM and 32K 16-bit words of ROM). 3.1.1 On-Chip Dual-Access RAM (DARAM) The DARAM is located in the byte address range 000000h−00FFFFh and is composed of eight blocks of 8K bytes each (see Table 3−1).
  • Page 32: On-Chip Read-Only Memory (Rom)

    CPU or peripherals cannot access the on-chip SROM memory space. This ROM block is not programmed on standard 5509 devices, but can be used to implement a custom, secure bootload feature. Contact your local Texas Instruments representative for more information on custom ROM programming.
  • Page 33: 3.1.5 Memory Map

    Functional Overview 3.1.5 Memory Map The 5509 provides 16M bytes of total memory space composed of on-cip RAM, on-chip ROM, and external memory space supporting a variety of memory types. The on-chip, dual-access RAM allows two accesses to a given block during the same cycle. The 5509 supports 8 blocks of 8K bytes of dual-access RAM. The on-chip, single-access RAM allows one access to a given block per clock cycle.
  • Page 34: Tms320Vc5509 Memory Map (Pge Package)

    # The minus 256K bytes consists of 32K-byte DARAM/HPI access, 32K-byte DARAM, and 192K-byte SARAM. || Read-only memory (ROM): one access every two cycles, two blocks of 32K bytes. Figure 3−3. TMS320VC5509 Memory Map (PGE Package) SPRS163H April 2001 − Revised January 2008...
  • Page 35: Tms320Vc5509 Memory Map (Ghh Package)

    # The minus 256K bytes consists of 32K-byte DARAM/HPI access, 32K-byte DARAM, and 192K-byte SARAM. || Read-only memory (ROM): one access every two cycles, two blocks of 32K bytes. Figure 3−4. TMS320VC5509 Memory Map (GHH Package) April 2001 − Revised January 2008...
  • Page 36: 3.1.6 Boot Configuration

    Functional Overview 3.1.6 Boot Configuration The on-chip bootloader provides a method to transfer application code and tables from an external source to the on-chip RAM memory at power up. These options include: • Enhanced host-port interface (HPI) in multiplexed or nonmultiplexed mode •...
  • Page 37: Peripherals

    Functional Overview Peripherals The 5509 supports the following peripherals: • A Configurable Parallel External Interface supporting either: − 16-bit external memory interface (EMIF) for asynchronous memory and/or SDRAM − 16-bit enhanced host-port interface (HPI) • A six-channel direct memory access (DMA) controller •...
  • Page 38: Dma Channel Control Register (Dma_Ccr)

    Functional Overview 3.3.1 DMA Channel Control Register (DMA_CCR) The channel control register (DMA_CCR) bit layouts are shown in Figure 3−5. DST AMODE SRC AMODE END PROG Reserved REPEAT AUTO INIT R/W, 00 R/W, 00 R/W, 0 R, 0 R/W, 0 R/W, 0 PRIO SYNC...
  • Page 39: I 2 C Interface

    † The I 2 C receive event (REVTI2C) and external interrupt 4 (INT4) share a synchronization input to the DMA. When the SYNC field of the DMA_CCR is set to 10011b, the logical OR of these two sources is used for DMA synchronization. C Interface The TMS320VC5509 includes an I C serial port. The I C port supports: •...
  • Page 40: Configurable External Buses

    Functional Overview Configurable External Buses The 5509 offers several combinations of configurations for its external parallel port and two serial ports. This allows the system designer to choose the appropriate media interface for its application without the need of a large-pin-count package. The External Bus Selection Register controls the routing of the parallel and serial port signals.
  • Page 41 Functional Overview Table 3−5. External Bus Selection Register Bit Field Description (Continued) BITS DESCRIPTION Bus keep enable. † (PG3.0 or later) BKE = 0: Bus keeper, pullups/pulldowns, and the USB I/O cells are enabled. BKE = 1: Bus keeper, pullups/pulldowns, and the USB I/O cells are disabled. EMIFX2 mode.
  • Page 42: 3.5.2 Parallel Port

    In addition, 5 control signals of the external parallel bus are used as general-purpose I/O. The external parallel port’s 14 (LQFP) or 16 (BGA) address signals are used as general-purpose I/O. Table 3−6. TMS320VC5509 Parallel Port Signal Routing Data EMIF (00) †...
  • Page 43: 3.5.3 Parallel Port Signal Routing

    Functional Overview 3.5.3 Parallel Port Signal Routing The 5509 allows access to 16-bit-wide (read and write) asynchronous memory and 16-bit-wide SDRAM. For 16-bit-wide memories, EMIF.A[0] is kept low and is not used. To provide as many address pins as possible, the 5509 routes the parallel port signals as shown in Figure 3−7.
  • Page 44: 3.5.4 Serial Ports

    McBSP mode: all six signals of the McBSP are routed to the six external signals of the serial port. • MMC/SD mode: all six signals of the MultiMedia Card/Secure Digital port are routed to the six external signals of the serial port. Table 3−7. TMS320VC5509 Serial Port1 Signal Routing MCBSP1 (00) † MMC/SD1 (10) † PIN SIGNAL McBSP1.CLKR...
  • Page 45: General-Purpose Input/Output (Gpio) Ports

    Functional Overview General-Purpose Input/Output (GPIO) Ports 3.6.1 Dedicated General-Purpose I/O The 5509 provides eight dedicated general-purpose input/output pins, GPIO0−GPIO7. Each pin can be indepedently configured as an input or an output using the I/O Direction Register (IODIR). The I/O Data Register (IODATA) is used to monitor the logic state of pins configured as inputs and control the logic state of pins configured as outputs.
  • Page 46: 3.6.2 Address Bus General-Purpose I/O

    Functional Overview IO5D Reserved IO7D IO6D IO4D IO3D IO2D IO1D IO0D (BGA) R−00000000 R/W−pin R/W−pin R/W−pin R/W−pin R/W−pin R/W−pin R/W−pin R/W−pin LEGEND: R = Read, W = Write, pin = value present on the pin (IO7−IO0 default to inputs after reset) Figure 3−10.
  • Page 47: Address/Gpio Direction Register (Agpiodir) Bit Layout

    Functional Overview AIODIR15 AIODIR14 AIODIR13 AIODIR12 AIODIR11 AIODIR10 AIODIR9 AIODIR8 (BGA) (BGA) R/W, 0 R/W, 0 R/W, 0 R/W, 0 R/W, 0 R/W, 0 R/W, 0 R/W, 0 AIODIR7 AIODIR6 AIODIR5 AIODIR4 AIODIR3 AIODIR2 AIODIR1 AIODIR0 R/W, 0 R/W, 0 R/W, 0 R/W, 0 R/W, 0...
  • Page 48: 3.6.3 Ehpi General-Purpose I/O

    Functional Overview 3.6.3 EHPI General-Purpose I/O Six control lines of the External Parallel Bus can also be set as general-purpose I/O when the Parallel Port Mode bit field of the External Bus Selection Register is set to Nonmultiplexed EHPI (10) or Multiplexed EHPI mode (11).
  • Page 49: System Register

    Functional Overview Reserved GPIOD13 GPIOD12 GPIOD11 GPIOD10 GPIOD9 GPIOD8 R, 0000 0000 00 R/W, 0 R/W, 0 R/W, 0 R/W, 0 R/W, 0 R/W, 0 LEGEND: R = Read, W = Write, n = value after reset Figure 3−16. EHPI GPIO Data Register (EHPIGPIODATA) Bit Layout Table 3−16.
  • Page 50: Memory-Mapped Registers

    Temporary Data Register 1 [15−0] − Temporary Data Register 2 [15−0] − Temporary Data Register 3 [15−0] AC2L − Accumulator 2 [15−0] AC2H − [31−16] AC2G − [39−32] TMS320C54x and C54x are trademarks of Texas Instruments. SPRS163H April 2001 − Revised January 2008...
  • Page 51 Functional Overview Table 3−17. CPU Memory-Mapped Registers (Continued) C55x C54x WORD ADDRESS DESCRIPTION BIT FIELD REGISTER REGISTER (HEX) − Coefficient Data Pointer [15−0] AC3L − Accumulator 3 [15−0] AC3H − [31−16] AC3G − [39−32] − Extended Data Page Pointer [6−0] MDP05 −...
  • Page 52: Peripheral Register Description

    Functional Overview Peripheral Register Description Each 5509 device has a set of memory-mapped registers associated with peripherals as listed in Table 3−18 through Table 3−36. Some registers use less than 16 bits. When reading these registers, unused bits are always read as 0. NOTE: The CPU access latency to the peripheral memory-mapped registers is 6 CPU cycles.
  • Page 53: Dma Configuration Registers

    Functional Overview Table 3−20. DMA Configuration Registers PORT ADDRESS RESET VALUE † REGISTER NAME DESCRIPTION (WORD) GLOBAL REGISTER 0x0E00 DMA_GCR[2:0] DMA Global Control Register xxxx xxxx xxxx x000 0x0E03 DMA_GTCR DMA Timeout Control Register CHANNEL #0 REGISTERS DMA Channel 0 Source Destination 0x0C00 DMA_CSDP0 0000 0000 0000 0000...
  • Page 54 Functional Overview Table 3−20. DMA Configuration Registers (Continued) PORT ADDRESS RESET VALUE † REGISTER NAME DESCRIPTION (WORD) CHANNEL #2 REGISTERS (CONTINUED) 0x0C43 DMA_CSR2[6:0] DMA Channel 2 Status Register xxxx xxxx xx00 0000 DMA Channel 2 Source Start Address Register 0x0C44 DMA_CSSA_L2 Undefined (lower bits)
  • Page 55 Functional Overview Table 3−20. DMA Configuration Registers (Continued) PORT ADDRESS RESET VALUE † REGISTER NAME DESCRIPTION (WORD) CHANNEL #4 REGISTERS (CONTINUED) DMA Channel 4 Destination Start Address Register 0x0C87 DMA_CDSA_U4 Undefined (upper bits) 0x0C88 DMA_CEN4 DMA Channel 4 Element Number Register Undefined 0x0C89 DMA_CFN4...
  • Page 56: Real-Time Clock Registers

    Functional Overview Table 3−21. Real-Time Clock Registers RESET VALUE † WORD ADDRESS REGISTER NAME DESCRIPTION 0x1800 RTCSEC Seconds Register 0000 0000 0000 0000 0x1801 RTCSECA Seconds Alarm Register 0000 0000 0000 0000 0x1802 RTCMIN Minutes Register 0000 0000 0000 0000 0x1803 RTCMINA Minutes Alarm Register...
  • Page 57: Multichannel Serial Port #0

    Functional Overview Table 3−24. Multichannel Serial Port #0 PORT ADDRESS RESET VALUE † REGISTER NAME DESCRIPTION (WORD) 0x2800 DRR2_0[15:0] Data Receive Register 2, McBSP #0 0000 0000 0000 0000 0x2801 DRR1_0[15:0] Data Receive Register 1, McBSP #0 0000 0000 0000 0000 0x2802 DXR2_0[15:0] Data Transmit Register 2, McBSP #0...
  • Page 58: Multichannel Serial Port #1

    Functional Overview Table 3−25. Multichannel Serial Port #1 PORT ADDRESS † REGISTER NAME DESCRIPTION RESET VALUE (WORD) 0x2C00 DRR2_1[15:0] Data Receive Register 2, McBSP #1 0000 0000 0000 0000 0x2C01 DRR1_1[15:0] Data Receive Register 1, McBSP #1 0000 0000 0000 0000 0x2C02 DXR2_1[15:0] Data Transmit Register 2, McBSP #1...
  • Page 59: Multichannel Serial Port #2

    Functional Overview Table 3−26. Multichannel Serial Port #2 PORT ADDRESS † REGISTER NAME DESCRIPTION RESET VALUE (WORD) 0x3000 DRR2_2[15:0] Data Receive Register 2, McBSP #2 0000 0000 0000 0000 0x3001 DRR1_2[15:0] Data Receive Register 1, McBSP #2 0000 0000 0000 0000 0x3002 DXR2_2[15:0] Data Transmit Register 2, McBSP #2...
  • Page 60: Gpio

    0010 0101 0000 0010 § 0x3804 Rev ID[15:0] Silicon Revision Identification ‡ Contains factory information not intended for users. § For additional information, see TMS320VC5509 Digital Signal Processor Silicon Errata (literature number SPRZ006). Table 3−29. I C Module Registers † WORD ADDRESS...
  • Page 61: Watchdog Timer Registers

    Functional Overview Table 3−30. Watchdog Timer Registers † WORD ADDRESS REGISTER NAME DESCRIPTION RESET VALUE 0x4000 WDTIM[15:0] WD Timer Counter Register 1111 1111 1111 1111 0x4001 WDPRD[15:0] WD Timer Period Register 1111 1111 1111 1111 0x4002 WDTCR[13:0] WD Timer Control Register 0000 0011 1100 1111 0x4003 WDTCR2[15:0]...
  • Page 62: Mmc/Sd2 Module Registers

    Functional Overview Table 3−32. MMC/SD2 Module Registers † WORD ADDRESS REGISTER NAME DESCRIPTION RESET VALUE 0x4C00 MMCFCLK[8:0] MMC Function Clock Control Register 0000 0000 0000 0111 0x4C01 MMCCTL[10:0] MMC Control Register 0000 0000 0000 0000 0x4C02 MMCCLK[8:0] MMC Clock Control Register 0000 0000 0000 1111 0x4C03 MMCST0[12:0]...
  • Page 63 Functional Overview Table 3−33. USB Module Registers (Continued) † WORD ADDRESS REGISTER NAME DESCRIPTION RESET VALUE DMA CONTEXTS (CONTINUED) 0x5848 DMAC_I1 Input Endpoint 1 DMA Context Register Undefined 0x5850 DMAC_I2 Input Endpoint 2 DMA Context Register Undefined 0x5858 DMAC_I3 Input Endpoint 3 DMA Context Register Undefined 0x5860 DMAC_I4...
  • Page 64: Analog-To-Digital Controller (Adc) Registers

    Functional Overview Table 3−33. USB Module Registers (Continued) † WORD ADDRESS REGISTER NAME DESCRIPTION RESET VALUE CONTROL AND STATUS REGISTERS (CONTINUED) 0x6797 IDMAGINT Input DMA Go Interrupt Register xxxx xxxx 0000 0000 0x6798 ODMAGINT Output DMA Go Interrupt Register xxxx xxxx 0000 0000 0x6799 IDMAMSK Input DMA Interrupt Mask Register...
  • Page 65: 3.10 Interrupts

    Functional Overview 3.10 Interrupts Vector-relative locations and priorities for all internal and external interrupts are shown in Table 3−37. Table 3−37. Interrupt Table SOFTWARE RELATIVE LOCATION † NAME (TRAP) PRIORITY FUNCTION EQUIVALENT (HEX BYTES) RESET SINT0 Reset (hardware and software) NMI ‡...
  • Page 66: Ifr And Ier Registers

    Functional Overview 3.10.1 IFR and IER Registers The IFR0 (Interrupt Flag Register 0) and IER0 (Interrupt Enable Register 0) bit layouts are shown in Figure 3−17. NOTE: Some of the interrupts are shared between multiple interrupt sources. All sources for a particular bit are internally combined using a logic OR function so that no additional user configuration is required to select the interrupt source.
  • Page 67: Interrupt Timing

    Functional Overview The IFR1 (Interrupt Flag Register 1) and IER1 (Interrupt Enable Register 1) bit layouts are shown in Figure 3−18. NOTE: It is possible to have active interrupts simultaneously from both the external interrupt 4 (INT4) and the real-time clock (RTC). When an interrupt is detected in this bit, the real-time clock status register should be polled to determine if the real-time clock is the source of the interrupt.
  • Page 68: Waking Up From Idle Condition

    Once out of IDLE, any system not using the USB should put the USB module in idle mode to reduce power consumption. For more details on the TMS320VC5509 oscillator-disable process, see the Disabling the Internal Oscillator on the TMS320VC5507/5509/5509A DSP application report (literature number SPRA078).
  • Page 69: Documentation Support

    TMS320 DSP customers on product information. Information regarding TI DSP products is also available on the Worldwide Web at http://www.ti.com uniform resource locator (URL). TMS320 and TMS320C5000 are trademarks of Texas Instruments. April 2001 − Revised January 2008 SPRS163H...
  • Page 70: Device And Development-Support Tool Nomenclature

    TMS320 DSP devices and support tools. Each TMS320 DSP commercial family member has one of three prefixes: TMX, TMP, or TMS. Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX / TMDX) through fully qualified production devices/tools (TMS / TMDS).
  • Page 71: Tms320Vc5509 Device Nomenclature

    DEVICE 55x DSP: 5509 † No silicon revision marked on the package indicates earlier (TMX or TMP) silicon. See the TMS320VC5509 Digital Signal Processor Silicon Errata (literature number SPRZ006) to identify TMX or TMP silicon revision. ‡ BGA = Ball Grid Array...
  • Page 72: Electrical Specifications

    Electrical Specifications Electrical Specifications This section provides the absolute maximum ratings and the recommended operating conditions for the TMS320VC5509 DSP. All electrical and switching characteristics in this data manual are valid over the recommended operating conditions unless otherwise specified. Absolute Maximum Ratings The list of absolute maximum ratings are specified over operating case temperature.
  • Page 73 Electrical Specifications Recommended Operating Conditions (Continued) UNIT X2/CLKIN DV DD + 0.3 DN and DP ‡ SDA & SCL: V DD related input levels † V IH V IH High-level input voltage, I/O High-level input voltage, I/O 0.7*DV DD DV DD (max) +0.5 All other inputs DV DD + 0.3 (including hysteresis inputs)
  • Page 74: Electrical Characteristics Over Recommended Operating Case Temperature Range

    Electrical Specifications Electrical Characteristics Over Recommended Operating Case Temperature Range (Unless Otherwise Noted) PARAMETER TEST CONDITIONS UNIT DV DD = 3.3 ± 0.3 V, DN, DP, and PU † I OH = −300 µA V OH V OH High-level output voltage High-level output voltage DV DD = 3.3 ±...
  • Page 75: V Test Load Circuit

    Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin. Figure 5−1. 3.3-V Test Load Circuit Package Thermal Resistance Characteristics Table 5−1 provides the estimated thermal resistance characteristics for the TMS320VC5509 DSP package types. Table 5−1. Thermal Resistance Characteristics...
  • Page 76: Timing Parameter Symbology

    Electrical Specifications Timing Parameter Symbology Timing parameter symbols used in the timing requirements and switching characteristics tables are created in accordance with JEDEC Standard 100. To shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows: Lowercase subscripts and their meanings: Letters and symbols and their meanings: access time...
  • Page 77: Clock Options

    Electrical Specifications Clock Options The frequency of the reference clock provided at the X2/CLKIN pin can be divided by a factor of two or four or multiplied by one of several values to generate the internal machine cycle. 5.6.1 Internal System Oscillator With External Crystal The internal oscillator is always enabled following a device reset.
  • Page 78: 5−3 Clkin Timing Requirements

    Electrical Specifications 5.6.2 Layout Considerations Since parasitic capacitance, inductance and resistance can be significant in any circuit, good PC board layout practices should always be observed when planning trace routing to the discrete components used in the oscillator circuit. Specifically, the crystal and the associated discrete components should be located as close to the DSP as physically possible.
  • Page 79: Bypass Mode Clock Timings

    Electrical Specifications X2/CLKIN CLKOUT NOTE A: The relationship of X2/CLKIN to CLKOUT depends on the PLL bypass divide factor chosen for the CLKMD register. The waveform relationship shown in Figure 5−3 is intended to illustrate the timing parameters based on CLKOUT = 1/2(CLKIN) configuration. Figure 5−3.
  • Page 80: External Multiply-By-N Clock Timings

    Electrical Specifications X2/CLKIN CLKOUT Bypass Mode NOTE A: The relationship of X2/CLKIN to CLKOUT depends on the PLL multiply and divide factor chosen for the CLKMD register. The waveform relationship shown in Figure 5−3 is intended to illustrate the timing parameters based on CLKOUT = 1xCLKIN configuration. Figure 5−4.
  • Page 81: 5−7 Asynchronous Memory Cycle Timing Requirements

    Electrical Specifications Memory Interface Timings 5.7.1 Asynchronous Memory Timings Table 5−7 and Table 5−8 assume testing over recommended operating conditions (see Figure 5−6 and Figure 5−7). Table 5−7. Asynchronous Memory Cycle Timing Requirements UNIT Setup time, read data valid before CLKOUT high † t su(DV-COH) t h(COH-DV) Hold time, read data valid after CLKOUT high...
  • Page 82: Asynchronous Memory Read Timings

    Electrical Specifications Extended Hold Hold = 2 Setup = 2 Strobe = 5 Not Ready = 2 CLKOUT † CEx ‡ A[20:0] § D[15:0] ARDY † CLKOUT is equal to CPU clock ‡ CEx becomes active depending on the memory address space being accessed §...
  • Page 83: Asynchronous Memory Write Timings

    Electrical Specifications Extended Setup = 2 Strobe = 5 Not Ready = 2 Hold = 1 Hold = 2 CLKOUT † CEx ‡ A[20:0] § D[15:0] ARDY † CLKOUT is equal to CPU clock ‡ CEx becomes active depending on the memory address space being accessed §...
  • Page 84: 5−9 Synchronous Dram Cycle Timing Requirements

    Electrical Specifications 5.7.2 Synchronous DRAM (SDRAM) Timings Table 5−9, Table 5−10, Table 5−11, and Table 5−12 assume testing over recommended operating conditions (see Figure 5−8 through Figure 5−13). Table 5−9. Synchronous DRAM Cycle Timing Requirements † [SDRAM Clock = 1X, (1/4)X, and (1/8)X of CPU Clock] UNIT t su(DV-CLKMEMH) Setup time, read data valid before CLKMEM high...
  • Page 85: 5−11 Synchronous Dram Cycle Timing Requirements [Sdram Clock = (1/2)X Of Cpu Clock]

    Electrical Specifications † Table 5−11. Synchronous DRAM Cycle Timing Requirements [SDRAM Clock = (1/2)X of CPU Clock] UNIT t su(DV-CLKMEMH) Setup time, read data valid before CLKMEM high t h(CLKMEMH-DV) Hold time, read data valid after CLKMEM high 13.88 ‡ t c(CLKMEM) Cycle time, CLKMEM †...
  • Page 86: Three Sdram Read Commands

    Electrical Specifications READ READ READ CLKMEM CEx † BEx ‡ EMIF.A[13:0] D[15:0] SDA10 SDRAS SDCAS SDWE † The chip enable that becomes active depends on the address being accessed. ‡ All BE[1:0] signals are driven low (active) during reads. Byte manipulation of the read data is performed inside the EMIF. These signals remain active until the next access that is not an SDRAM read occurs.
  • Page 87: Three Sdram Wrt Commands

    Electrical Specifications WRITE WRITE WRITE CLKMEM CEx † BEx ‡ EMIF.A[13:0] D[15:0] SDA10 SDRAS SDCAS SDWE † The chip enable that becomes active depends on the address being accessed. ‡ All BE[1:0] signals are driven low (active) during reads. Byte manipulation of the read data is performed inside the EMIF. These signals remain active until the next access that is not an SDRAM read occurs.
  • Page 88: Sdram Actv Command

    Electrical Specifications ACTV CLKMEM CEx † BEx ‡ EMIF.A[13:0] Bank Activate/Row Address D[15:0] SDA10 SDRAS SDCAS SDWE † The chip enable that becomes active depends on the address being accessed. ‡ All BE[1:0] signals are driven low (active) during reads. Byte manipulation of the read data is performed inside the EMIF. These signals remain active until the next access that is not an SDRAM read occurs.
  • Page 89: Sdram Dcab Command

    Electrical Specifications DCAB CLKMEM CEx † BEx ‡ EMIF.A[13:0] D[15:0] SDA10 SDRAS SDCAS SDWE † The chip enable that becomes active depends on the address being accessed. ‡ All BE[1:0] signals are driven low (active) during reads. Byte manipulation of the read data is performed inside the EMIF. These signals remain active until the next access that is not an SDRAM read occurs.
  • Page 90: Sdram Refr Command

    Electrical Specifications REFR CLKMEM CEx † BEx ‡ EMIF.A[13:0] D[15:0] SDA10 SDRAS SDCAS SDWE † The chip enable that becomes active depends on the address being accessed. ‡ All BE[1:0] signals are driven low (active) during reads. Byte manipulation of the read data is performed inside the EMIF. These signals remain active until the next access that is not an SDRAM read occurs.
  • Page 91: Sdram Mrs Command

    Electrical Specifications CLKMEM CEx † BEx ‡ MRS Value 0x30 § EMIF.A[13:0] D[15:0] SDA10 SDRAS SDCAS SDWE † The chip enable that becomes active depends on the address being accessed. ‡ All BE[1:0] signals are driven low (active) during reads. Byte manipulation of the read data is performed inside the EMIF. These signals remain active until the next access that is not an SDRAM read occurs.
  • Page 92: Power-Up Reset (On-Chip Oscillator Active) Timings

    Electrical Specifications Reset Timings 5.8.1 Power-Up Reset (On-Chip Oscillator Active) Table 5−13 assumes testing over recommended operating conditions (see Figure 5−14). Table 5−13. Power-Up Reset (On-Chip Oscillator Active) Timing Requirements UNIT Hold time, RESET low after oscillator stable † 3P ‡ t h(SUPSTBL-RSTL) †...
  • Page 93: 5−16 Reset Timing Requirements

    Electrical Specifications 5.8.3 Warm Reset Table 5−16 and Table 5−17 assume testing over recommended operating conditions (see Figure 5−16). Table 5−16. Reset Timing Requirements UNIT 3P † t w(RSL) Pulse width, reset low † P = 1/CPU clock frequency in ns. For example, when running parts at 144 MHz, use P = 6.94 ns. †...
  • Page 94: 5−18 External Interrupt Timing Requirements

    Electrical Specifications External Interrupt Timings Table 5−18 assumes testing over recommended operating conditions (see Figure 5−17). † Table 5−18. External Interrupt Timing Requirements UNIT t w(INTL)A Pulse width, interrupt low, CPU active t w(INTH)A Pulse width, interrupt high, CPU active †...
  • Page 95: 5−20 Xf Switching Characteristics

    Electrical Specifications 5.11 XF Timings Table 5−20 assumes testing over recommended operating conditions (see Figure 5−19). Table 5−20. XF Switching Characteristics PARAMETER UNIT Delay time, CLKOUT high to XF high t d(XF) t d(XF) Delay time, CLKOUT high to XF low CLKOUT †...
  • Page 96: 5−21 Gpio Pins Configured As Inputs Timing Requirements

    Electrical Specifications 5.12 General-Purpose Input/Output (GPIO ) Timings Table 5−21 and Table 5−22 assume testing over recommended operating conditions (see Figure 5−20). Table 5−21. GPIO Pins Configured as Inputs Timing Requirements UNIT GPIO AGPIO † t su(GPIO-COH) t su(GPIO-COH) Setup time, IOx input valid before CLKOUT high Setup time, IOx input valid before CLKOUT high EHPIGPIO ‡...
  • Page 97: 5−23 Tin/Tout Pins Configured As Inputs Timing Requirements

    Electrical Specifications 5.13 TIN/TOUT Timings (Timer0 Only) Table 5−23 and Table 5−24 assume testing over recommended operating conditions (see Figure 5−21 and Figure 5−22). †‡ Table 5−23. TIN/TOUT Pins Configured as Inputs Timing Requirements UNIT t w(TIN/TOUTL) Pulse width, TIN/TOUT low 2P + 1 t w(TIN/TOUTH) Pulse width, TIN/TOUT high...
  • Page 98: 5−25 Mcbsp Transmit And Receive Timing Requirements

    Electrical Specifications 5.14 Multichannel Buffered Serial Port (McBSP) Timings 5.14.1 McBSP Transmit and Receive Timings Table 5−25 and Table 5−26 assume testing over recommended operating conditions (see Figure 5−23 and Figure 5−24). † ransmit and Receive Table 5−25. McBSP T Timing Requirements UNIT 2P ‡...
  • Page 99: 5−26 Mcbsp Transmit And Receive Switching Characteristics

    Electrical Specifications †‡ Transmit and Receive Table 5−26. McBSP Switching Characteristics PARAMETER UNIT t c(CKRX) Cycle time, CLKR/X CLKR/X int D−1 § D+1 § MC11 t w(CKRXH) Pulse duration, CLKR/X high CLKR/X int C−1 § C+1 § MC12 t w(CKRXL) Pulse duration, CLKR/X low CLKR/X int CLKR int...
  • Page 100: Mcbsp Receive Timings

    Electrical Specifications MC2, MC11 MC2, MC12 CLKR MC13 MC13 FSR (Int) FSR (Ext) Bit (n−1) (n−2) (n−3) (n−4) (RDATDLY=00b) Bit (n−1) (n−2) (n−3) (RDATDLY=01b) Bit (n−1) (n−2) (RDATDLY=10b) Figure 5−23. McBSP Receive Timings MC2, MC11 MC2, MC12 CLKX MC14 MC14 FSX (Int) MC10 FSX (Ext)
  • Page 101: 5−27 Mcbsp General-Purpose I/O Timing Requirements

    Electrical Specifications 5.14.2 McBSP General-Purpose I/O Timings Table 5−27 and Table 5−28 assume testing over recommended operating conditions (see Figure 5−25). Table 5−27. McBSP General-Purpose I/O Timing Requirements UNIT Setup time, MGPIOx input mode before CLKOUT high † 2P+7 ‡ MC20 t su(MGPIO-COH) Hold time, MGPIOx input mode after CLKOUT high †...
  • Page 102: 5−29 Mcbsp As Spi Master Or Slave Timing Requirements (Clkstp = 10B, Clkxp = 0)

    Electrical Specifications 5.14.3 McBSP as SPI Master or Slave Timings Table 5−29 to Table 5−36 assume testing over recommended operating conditions (see Figure 5−26 through Figure 5−29). ‡ † Table 5−29. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) MASTER SLAVE UNIT...
  • Page 103: Mcbsp Timings As Spi Master Or Slave: Clkstp = 10B, Clkxp = 0

    Electrical Specifications MC25 MC26 CLKX MC28 MC29 MC27 MC31 MC32 MC30 Bit 0 Bit (n−1) (n−2) (n−3) (n−4) MC23 MC24 Bit 0 Bit (n−1) (n−2) (n−3) (n−4) Figure 5−26. McBSP Timings as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 April 2001 −...
  • Page 104: 5−31 Mcbsp As Spi Master Or Slave Timing Requirements (Clkstp = 11B, Clkxp = 0)

    Electrical Specifications ‡ † Table 5−31. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) MASTER SLAVE UNIT UNIT MC33 t su(DRV-CKXH) Setup time, DR valid before CLKX high 2 − 8P MC34 t h(CKXH-DRV) Hold time, DR valid after CLKX high 2 + 8P MC25 t su(FXL-CKXH)
  • Page 105: 5−33 Mcbsp As Spi Master Or Slave Timing Requirements (Clkstp = 10B, Clkxp = 1)

    Electrical Specifications ‡ † Table 5−33. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) MASTER SLAVE UNIT UNIT MC33 t su(DRV-CKXH) Setup time, DR valid before CLKX high 2 − 8P MC34 t h(CKXH-DRV) Hold time, DR valid after CLKX high 2 + 8P MC36 t su(FXL-CKXL)
  • Page 106: 5−35 Mcbsp As Spi Master Or Slave Timing Requirements (Clkstp = 11B, Clkxp = 1)

    Electrical Specifications ‡ † Table 5−35. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) MASTER SLAVE UNIT UNIT MC23 t su(DRV-CKXL) Setup time, DR valid before CLKX low 2 − 8P MC24 t h(CKXL-DRV) Hold time, DR valid after CLKX low 2 + 8P MC36 t su(FXL-CKXL)
  • Page 107: 5−37 Ehpi Timing Requirements

    Electrical Specifications 5.15 Enhanced Host-Port Interface (EHPI) Timings Table 5−37 and Table 5−38 assume testing over recommended operating conditions (see Figure 5−30 through Figure 5−34). Table 5−37. EHPI Timing Requirements UNIT t su(HASL-HDSL) Setup time, HAS low before HDS low t h(HDSL-HASL) Hold time, HAS low after HDS low Setup time, (HR/W, HBE[1:0], HPI.HA[13:0],...
  • Page 108: Ehpi Nonmultiplexed Read/Write Timings

    Electrical Specifications Read Write HR/W HCNTL[0] Valid Valid HBE[1:0] HPI.HA[13:0] Valid Valid HPI.HD[15:0] Read Data (Read) HPI.HD[15:0] Write Data (Write) HRDY NOTES: A. Any non-multiplexed access with HCNTL0 low will result in HPIC register access. For data read or write, HCNTL0 must stay high during the EHPI access.
  • Page 109: Ehpi Multiplexed Memory (Hpid) Access Read/Write Timings Without Autoincrement

    Electrical Specifications Read Write HR/W HBE[1:0] HCNTL[1:0] Valid (11) Valid (11) HPI.HD[15:0] Read Data (Read) HPI.HD[15:0] Write Data (Write) HRDY NOTE: The falling edge of HCS must occur concurrent with or before the falling edge of HDS. The rising edge of HCS must occur concurrent with or after the rising edge of HDS.
  • Page 110: Ehpi Multiplexed Memory (Hpid) Access Read Timings With Autoincrement

    Electrical Specifications HR/W HBE[1:0] HCNTL[1:0] Valid (01) Valid (01) HPI.HD[15:0] Read Data Read Data (Read) HRDY HPIA Contents HPID d(n) d(n+1) d(n+2) Contents NOTES: A. During autoincrement mode, although the EHPI internally increments the memory address, reads of the HPIA register by the host will always indicate the base address.
  • Page 111: Ehpi Multiplexed Memory (Hpid) Access Write Timings With Autoincrement

    Electrical Specifications HR/W HBE[1:0] HCNTL[1:0] Valid (01) Valid (01) HPI.HD[15:0] Write Data Write Data (Write) HRDY HPIA Contents HPID d(n) d(n+1) d(n+2) Contents NOTES: A. During autoincrement mode, although the EHPI internally increments the memory address, reads of the HPIA register by the host will always indicate the base address.
  • Page 112: Ehpi Multiplexed Register Access Read/Write Timings

    Electrical Specifications Read Write HR/W HBE[1:0] Valid (10 or 00) Valid (10 or 00) HCNTL[1:0] HPI.HD[15:0] Read Data (Read) HPI.HD[15:0] Write Data (Write) HRDY NOTE: The falling edge of HCS must occur concurrent with or before the falling edge of HDS. The rising edge of HCS must occur concurrent with or after the rising edge of HDS.
  • Page 113: 5−39 I 2 C Signals (Sda And Scl) Timing Requirements

    Electrical Specifications 5.16 I C Timings Table 5−39 and Table 5−40 assume testing over recommended operating conditions (see Figure 5−35 and Figure 5−36). Table 5−39. I C Signals (SDA and SCL) Timing Requirements STANDARD FAST MODE MODE UNIT UNIT µs t c(SCL) Cycle time, SCL Setup time, SCL high before SDA low for a repeated START...
  • Page 114: 5−40 I 2 C Signals (Sda And Scl) Switching Characteristics

    Electrical Specifications Table 5−40. I C Signals (SDA and SCL) Switching Characteristics STANDARD FAST MODE MODE PARAMETER PARAMETER UNIT UNIT µs IC16 t c(SCL) Cycle time, SCL Delay time, SCL high to SDA low for a repeated START µs IC17 t d(SCLH-SDAL) condition Delay time, SDA low to SCL low for a START and a repeated...
  • Page 115: 5−41 Multimedia Card (Mmc) Timing Requirements

    Electrical Specifications 5.17 MultiMedia Card (MMC) Timings Table 5−41 and Table 5−42 assume testing over recommended operating conditions (see Figure 5−37). Table 5−41. MultiMedia Card (MMC) Timing Requirements UNIT MMC7 t su(DV-CLKH) Setup time, data valid before clock high MMC8 t h(CLKH-DV) Hold time, data valid after clock high Table 5−42.
  • Page 116: 5−43 Secure Digital (Sd) Card Timing Requirements

    Electrical Specifications 5.18 Secure Digital (SD) Card Timings Table 5−43 and Table 5−44 assume testing over recommended operating conditions (see Figure 5−38). Table 5−43. Secure Digital (SD) Card Timing Requirements UNIT t su(DV-CLKH) Setup time, data valid before clock high t h(CLKH-DV) Hold time, data valid after clock high Table 5−44.
  • Page 117: 5−45 Universal Serial Bus (Usb) Characteristics

    Electrical Specifications 5.19 Universal Serial Bus (USB) Timings Table 5−45 assumes testing over recommended operating conditions (see Figure 5−39 and Figure 5−40). Table 5−45. Universal Serial Bus (USB) Characteristics FULL SPEED 12Mbps PARAMETER PARAMETER UNIT UNIT Rise time of DP and DN signals † Fall time of DP and DN signals †...
  • Page 118: Full-Speed Loads

    Electrical Specifications 5509 USBV DD R(PU) 1.5 kW D− NOTES: A. A full-speed buffer is measured with the load shown. B. C L = 50 pF Figure 5−40. Full-Speed Loads SPRS163H April 2001 − Revised January 2008...
  • Page 119: 5−46 Adc Characteristics

    Electrical Specifications 5.20 ADC Timings Table 5−46 assumes testing over recommended operating conditions. Table 5−46. ADC Characteristics PARAMETER UNIT t c(SCLC) Cycle time, ADC internal conversion clock µs t d(AQ) Delay time, ADC sample and hold acquisition time t d(CONV) Delay time, ADC conversion time 13 * t c(SCLC) Static differential non-linearity error...
  • Page 120: Mechanical Data

    Mechanical Data Mechanical Data The following mechanical package diagram(s) reflect the most current released mechanical data available for the designated device(s). SPRS163H April 2001 − Revised January 2008...
  • Page 121: Packaging Information

    PACKAGE OPTION ADDENDUM www.ti.com 7-Apr-2009 PACKAGING INFORMATION Orderable Device Status Package Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Type Drawing TMS320VC5509GHH31 OBSOLETE BGA MI Call TI Call TI CROSTA TMS320VC5509PGE31 OBSOLETE LQFP Call TI Call TI The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
  • Page 122 MECHANICAL DATA MTQF017A – OCTOBER 1994 – REVISED DECEMBER 1996 PGE (S-PQFP-G144) PLASTIC QUAD FLATPACK 0,27 0,08 0,17 0,50 0,13 NOM Gage Plane 17,50 TYP 20,20 19,80 0,25 0,05 MIN 22,20 0 – 7 21,80 0,75 0,45 1,45 1,35 Seating Plane 0,08 1,60 MAX 4040147 / C 10/96...
  • Page 124 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.

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