Bus Protocol; Ieee 1149.1 Standard - Texas Instruments TMS320C6000 Reference Manual

2

Bus Protocol

The IEEE 1149.1 specification covers the requirements for the test access port
(TAP) bus slave devices and provides certain rules, summarized as follows:
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When these devices are daisy-chained together, the TDO of one device has
approximately a half TCK cycle setup to the next device's TDI signal. This type
of timing scheme minimizes race conditions that would occur if both TDO and
TDI were timed from the same TCK edge. The penalty for this timing scheme
is a reduced TCK frequency.
The IEEE 1149.1 specification does not provide rules for bus master (emula-
tor) devices. Instead, it states that it expects a bus master to provide bus slave
compatible timings. The XDS510 provides timings that meet the bus slave
rules.
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IEEE 1149.1 Standard

For more information concerning the IEEE 1149.1 standard, contact IEEE
Customer Service:
Address:
IEEE Customer Service
445 Hoes Lane, PO Box 1331
Piscataway, NJ 08855-1331
Phone:
in the US and Canada: (800) 678−IEEE
outside the US and Canada: (908) 981−1393
FAX: (908) 981−9667
Telex:
SPRU641
Designing Your Target System's Emulator Connector (14-Pin Header)
The TMS/TDI inputs are sampled on the rising edge of the TCK signal of
the device.
The TDO output is clocked from the falling edge of the TCK signal of the
device.
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Bus Protocol / IEEE 1149.1 Standard
Designing for JTAG Emulation 5