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TMS320C6201
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004
timing requirements for McBSP
NO
NO.
2
t
Cycle time, CLKR/X
c(CKRX)
3
t
Pulse duration, CLKR/X high or CLKR/X low
w(CKRX)
5
5
t
t
Setup time, external FSR high before CLKR low
Setup time external FSR high before CLKR low
su(FRH-CKRL)
6
6
t
t
Hold time, external FSR high after CLKR low
Hold time external FSR high after CLKR low
h(CKRL-FRH)
7
7
t
t
Setup time, DR valid before CLKR low
Setup time DR valid before CLKR low
su(DRV-CKRL)
8
8
t
t
Hold time DR valid after CLKR low
Hold time, DR valid after CLKR low
h(CKRL-DRV)
10
10
t
t
Setup time external FSX high before CLKX low
Setup time, external FSX high before CLKX low
su(FXH-CKXL)
11
11
t
t
Hold time, external FSX high after CLKX low
Hold time external FSX high after CLKX low
h(CKXL-FXH)
†
CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
‡
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
§
The maximum bit rate for the C6202/02B/03 device is 100 Mbps or CPU/2 (the slower of the two). Care must be taken to ensure that the AC timings
specified in this data sheet are met. The maximum bit rate for McBSP-to-McBSP communications is 100 MHz; therefore, the minimum CLKR/X
clock cycle is either twice the CPU cycle time (2P), or 10 ns (100 MHz), whichever value is larger. For example, when running parts at 200 MHz
(P = 5 ns), use 10 ns as the minimum CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). When running
parts at 100 MHz (P = 10 ns), use 2P = 20 ns (50 MHz) as the minimum CLKR/X clock cycle. The maximum bit rate for McBSP-to-McBSP
communications applies when the serial port is a master of the clock and frame syncs (with CLKR connected to CLKX, FSR connected to FSX,
CLKXM = FSXM = 1, and CLKRM = FSRM = 0) in data delay 1 or 2 mode (R/XDATDLY = 01b or 10b) and the other device the McBSP
communicates to is a slave.
¶
The minimum CLKR/X pulse duration is either (P--1) or 4 ns, whichever is larger. For example, when running parts at 200 MHz (P = 5 ns), use
4 ns as the minimum CLKR/X pulse duration. When running parts at 100 MHz (P = 10 ns), use (P--1) = 9 ns as the minimum CLKR/X pulse
duration.
50
MULTICHANNEL BUFFERED SERIAL PORT TIMING
†‡
(see Figure 34)
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77251--1443
- -200
MIN
MAX
§
CLKR/X ext
2P
¶
CLKR/X ext
P -- 1
CLKR int
9
CLKR ext
2
CLKR int
6
CLKR ext
3
CLKR int
8
CLKR ext
0
CLKR int
3
CLKR ext
4
CLKX int
9
CLKX ext
2
CLKX int
6
CLKX ext
3
UNIT
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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