Iullcr - Instruction Unit Live Lock Control Register - IBM A2 User Manual

User's Manual
A2 Processor

14.5.61 IULLCR - Instruction Unit Live Lock Control Register

Register Short Name:
Decimal SPR Number:
Initial Value:
Slow SPR:
Guest Supervisor Mapping:
Bits Field Name
32:45 ///
46:49 LL_TRIG_DLY
50:53 ///
54:59 LL_HOLD_DLY
60:62 ///
63 IULL_EN
Alphabetical Register Listing
Page 612 of 897
IULLCR
892
0x0000000000020040
Y
Initial
Value
0x0 Reserved
0b1000 IU Live Lock Trigger Delay
Sets the number of cycles between events:
0000 Reserved
0001 16,384 - 18,368
0010 32,768 - 35,776
0011 49,152 - 53,184
0100 65,536 - 70,592
0101 81,920 - 88,000
0110 98,304 - 105,408
0111 114,688 - 122,816
1000 131,072 - 140,224
1001 147,456 - 157,632
1010 163,840 - 175,040
1011 180,224 - 192,448
1100 196,608 - 209,856
1101 212,992 - 227,264
1110 229,376 - 244,672
1111 245,760 - 262,080
0b0000 Reserved
0x4 IU Live Lock Hold Delay
Sets the length of time that threads are held. Hold time is equal to 16the encode in this
field. 0 is reserved.
0b000 Reserved
0b0 IU Live Lock Buster Enable
When enabled, every TRIG_DLY cycles instruction issue is disabled for HOLD_DLY
cycles. Once HOLD_DLY is complete, issue priority is randomized and instruction issue
resumes. Bits from the IULFSR are used to provide some variability in the trigger delay
time.
Read Access:
Write Access:
Duplicated for Multithread:
Notes:
Scan Ring:
Description
Hypv
Hypv
N
ccfg
Version 1.3
October 23, 2012