Watchdog Timer; Table 9-7. Watchdog Timer Period Selection - IBM A2 User Manual

When a fixed interval timer exception occurs, the exception status is recorded by setting the Fixed interval
Timer Interrupt Status (FIS) field of the TSR to 1. A fixed interval timer interrupt occurs if it is enabled by both
the Fixed Interval Timer Interrupt Enable (FIE) field of the TCR and by either MSR[EE] or MSR[GS].
Section 7.6.12 Fixed-Interval Timer Interrupt on page 344 provides more information about the handling of
Fixed Interval Timer interrupts.
The fixed interval timer interrupt handler software should clear TSR[FIS] before re-enabling MSR[EE] or
MSR[GS], to avoid another fixed interval timer interrupt due to the same exception (unless TCR[FIE] is
cleared instead).

9.5 Watchdog Timer

The watchdog timer provides a method for system error recovery in the event that the program running on the
A2 core has stalled and cannot be interrupted by the normal interrupt mechanism. The watchdog timer can be
configured to cause a critical-class watchdog timer interrupt upon the expiration of a single period of the
watchdog timer. It can also be configured to invoke a core-initiated reset upon the expiration of a second
period of the watchdog timer.
A watchdog timer exception occurs on a 01 transition of a selected bit from the time base. Note that a
watchdog timer exception also occurs if the selected time base bit transitions from 01 due to an mtspr
instruction that writes 1 to that time base bit when its previous value was 0.
The Watchdog Timer Period (WP) field of the TCR selects one of 4 bits from the time base, as shown in
Table 9-7.

Table 9-7. Watchdog Timer Period Selection

TCR[WP] Time Base Bit
0b00
0b01
0b10
0b11
The action taken upon a watchdog timer time-out depends upon the status of the Enable Next Watchdog
(ENW) and Watchdog Timer Interrupt Status (WIS) fields of the TSR at the time of the time-out. When
TSR[ENW] = 0, the next watchdog timer exception is "disabled", and the only action to be taken upon the
watchdog timer time-out is to set TSR[ENW] to 1. By clearing TSR[ENW], software can guarantee that the
time until the next enabled watchdog timer exception is at least one full Watchdog Timer period (and a
maximum of two full watchdog timer periods).
When TSR[ENW] = 1, the next watchdog timer exception is enabled, and the action to be taken upon the
time-out depends on the value of TSR[WIS]. If TSR[WIS] = 0, then the action is to set TSR[WIS] to 1, at which
time a watchdog timer interrupt occurs if enabled by both the Watchdog Timer Interrupt Enable (WIE) field of
the TCR and by either the Critical Interrupt Enable (CE) or Guest State (GS) fields of the MSR. The watchdog
timer interrupt handler software should clear TSR[WIS] before re-enabling MSR[CE] or MSR[GS], to avoid
another watchdog timer interrupt due to the same exception (unless TCR[WIE] is cleared instead).
Section 7.6.13 Watchdog Timer Interrupt on page 344 provides more information about the handling of
watchdog timer interrupts.
Version 1.3
October 23, 2012
Period
(Time Base Clocks)
19
TBL 2 clocks
13
23
TBL 2 clocks
9
25
TBL 2 clocks
7
31
TBL 2 clocks
1
Period Period
(32 MHz Clock) (1.6 GHz Clock)
327.68 s
16.38 ms
262.14 ms 5.24 ms
1.05 s 20.97 ms
67.11 s 1.34 s
User's Manual
A2 Processor
Period
(2.3 GHz Clock)
227.95 s
3.65 ms
14.59 ms
.93 s
Timer Facilities
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