Partially Executed Instructions - IBM A2 User Manual

Programming Note: In general, at process switch, due to possible process interlocks and possible data
availability requirements, the operating system needs to consider executing the following instructions:
• stwcx. or stdcx, to clear the reservation if one is outstanding, to ensure that an lwarx in the "old" process
is not paired with an stwcx. or stdcx in the "new" process. See the instruction descriptions for lwarx,
ldarx, stwcx. and stdcx in the Power ISA specification for more information about storage reservations.
• msync, to ensure that all storage operations of an interrupted process are complete with respect to other
processors before that process begins executing on another processor.
• isync, rfi, rfci, rfgi, or rfmci, to ensure that the instructions in the "new" process execute in the "new"
context.

7.4.1 Partially Executed Instructions

In general, the architecture permits load and store instructions to be partially executed, interrupted, and then
to be restarted from the beginning upon return from the interrupt. To guarantee that a particular load or store
instruction will complete without being interrupted and restarted, software must mark the storage being
referred to as guarded, and must use an elementary (not a string or multiple) load or store that is aligned on
an operand-sized boundary.
To guarantee that load and store instructions can, in general, be restarted and completed correctly without
software intervention, the following rules apply when an instruction is partially executed and then interrupted:
• For an elementary load, no part of the target register (GPR(RT), FPR(FRT), or auxiliary processor regis-
ter) will have been altered.
• For the "update" forms of load and store instructions, the update register, GPR(RA), will not have been
altered.
On the other hand, the following effects are permissible when certain instructions are partially executed and
then restarted:
• For any store instruction, some of the bytes at the addressed storage location might have been accessed
or updated (if write access to that page in which bytes were altered is permitted by the access control
mechanism). In addition, if the address for an stwcx. instruction is not aligned on a word boundary or the
address for an stdcx. instruction is not aligned on a doubleword boundary, the value in CR[CR0] is unde-
fined. It is also undefined whether or not the reservation (if one existed) has been cleared.
• For any load, some of the bytes at the addressed storage location might have been accessed (if read
access to that page in which bytes were accessed is permitted by the access control mechanism). In
addition, if the address for an lwarx instruction is not aligned on a word boundary or the address for an
ldarx instruction is not aligned on a doubleword boundary, it is undefined whether or not a reservation
has been set.
• For load multiple and load string instructions, some of the registers in the range to be loaded might have
been altered. Including the addressing registers (GPR[RA] and possibly GPR[RB]) in the range to be
loaded is an invalid form of these instructions (and a programming error). Thus, the rules for partial exe-
cution do not protect against overwriting of these registers. Such possible overwriting of the addressing
registers makes these invalid forms of load multiple and load strings inherently nonrestartable.
In no case will access control be violated.
Version 1.3
October 23, 2012
User's Manual
A2 Processor
CPU Interrupts and Exceptions
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