Tcr - Timer Control Register - IBM A2 User Manual

14.5.114 TCR - Timer Control Register

Register Short Name:
Decimal SPR Number:
Initial Value:
Slow SPR:
Guest Supervisor Mapping:
Bits Field Name
32:33 WP
34:35 WRC
36 WIE
37 DIE
38:39 FP
40 FIE
41 ARE
42 UDIE
Version 1.3
October 23, 2012
TCR
340
0x0000000000000000
N
Initial
Value
0b00 Watchdog Timer Period
Specifies one of four bit locations of the time base used to signal a watchdog timer excep-
tion on a transition from 0 to 1.
19
00 2 time base clocks.
23
01 2 time base clocks.
25
10 2 time base clocks.
31
11 2 time base clocks.
0b00 Watchdog Timer Reset Control
00 NoReset: No watchdog timer reset request will occur.
01 Reset1 request.
10 Reset2 request.
11 Reset3 request.
Note:
• Type of reset request to cause upon watchdog timer exception with TSR[ENW,WIS] =
0b11.
• These bits are set only by software. After a 1 has been written to one of these bits,
that bit remains a 1 until a reset request occurs. This is to prevent errant code from
disabling the watchdog reset function.
0b0 Watchdog Timer Interrupt Enable
0 Disable watchdog timer interrupt.
1 Enable watchdog timer interrupt.
0b0 Decrementer Interrupt Enable
0 Disable decrementer interrupt.
1 Enable decrementer interrupt.
0b00 Fixed-Interval Timer Period
Specifies one of four bit locations of the time base used to signal a fixed-interval timer
exception on a transition from 0 to 1.
11
00 2 time base clocks.
15
01 2 time base clocks.
19
10 2 time base clocks.
23
11 2 time base clocks.
0b0 Fixed-Interval Timer Interrupt Enable
0 Disable fixed interval timer interrupt.
1 Enable fixed interval timer interrupt.
0b0 Auto-Reload Enable
0 Disable auto reload.
1 Enable auto reload.
0b0 User Decrementer Interrupt Enable
0 Disable user decrementer interrupt.
1 Enable user decrementer interrupt.
Read Access:
Write Access:
Duplicated for Multithread:
Notes:
Scan Ring:
Description
User's Manual
A2 Processor
Hypv
Hypv
Y
AM
func
Alphabetical Register Listing
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