IBM A2 User Manual page 340

User's Manual
A2 Processor
• An instruction that is disabled:
– attn and CCR[EN_ATTN] = 0.
– msgsnd or msgclr and CCR2[EN_PC] = 0.
– icswx or icswepx and CCR2[EN_ICSWX] = 0.
• An illegal form of other defined instructions:
– store with update instruction with RA = 0.
– load with update instruction and RA = 0 or RA = RT.
– lswx instruction, and RA or RB is in the range of registers to be loaded, including the case in which
RA = 0, or RT = RA, or RT = RB.
– lmw, lswi, lswx, and RA is in the range of registers to be loaded.
– lswx, and RB is in the range of registers to be loaded.
– sc instruction with LEV > 1.
See Instruction Categories on page 86 for more information about the A2 core support for defined and allo-
cated instructions.
Privileged Instruction Exception
A privileged instruction exception occurs when MSR[PR] = 1 and execution is attempted of any of the
following kinds of instructions:
• A privileged instruction.
• An mtspr or mfspr instruction that specifies an SPRN value with SPRN
ble). A privileged instruction exception occurs regardless of whether or not the SPR referenced by the
SPRN value is defined.
Unimplemented Operation Exception
An unimplemented operation exception occurs when an instruction that is microcoded is executed and
CCR2[UCODE_DIS] = 1.
Trap Exception
A trap exception occurs when any of the conditions specified in a tw, twi, or td, tdi instruction are met.
However, if trap debug events are enabled (DBCR0[TRAP] = 1), internal debug mode is enabled
(DBCR0[IDM] = 1), and debug interrupts are enabled (MSR[DE] = 1), then a trap exception causes a debug
interrupt to occur rather than a program interrupt.
See Debug Facilities on page 399 for more information about Trap debug events.
Floating-Point Enabled Exception
A floating-point enabled exception occurs when the execution or attempted execution of a defined floating-
point instruction causes FPSCR[FEX] to be set to 1 in an attached floating-point unit. FPSCR[FEX] is the
Floating-Point Enabled Exception Summary bit in the Floating-Point Status and Control Register.
CPU Interrupts and Exceptions
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