IBM A2 User Manual page 168

User's Manual
A2 Processor
13. Initialize the MSR to enable interrupts as desired.
a. Set MSR[CE] to enable or disable critical input, watchdog timer, guest processor doorbell critical, and
processor doorbell critical interrupts.
b. Set MSR[EE] to enable or disable external input, decrementer, fixed interval timer, processor door-
bell, guest processor doorbell, and embedded performance monitor interrupts.
c. Set MSR[DE] to enable or disable debug interrupts.
d. Set MSR[ME] to enable or disable machine check interrupts.
e. Context synchronize to establish the new MSR context (isync).
14. Initialize any other processor core resources as required by the system (GPRs, SPRGs, and so on).
15. Initialize the fault isolation register masks to enable error reporting.
a. Clear the Fault Isolation Registers (SCOM access to FIR0, FIR1 and FIR2) to remove any error bits
that might have been inadvertently set. Even though the Fault Isolation Registers should have been
initialized to 0s during the POR scan sequence, this action ensures that no FIR bits are active before
enabling error reporting.
b. Clear the fault isolation register masks (SCOM access to FIR0M, FIR1M, and FIR2M). This removes
masking of the corresponding FIR error bits and enables error reporting outside of the core through
the chip level error facilities.
16. Initialize any other facilities outside the processor core as required by the system.
17. Initialize system memory as required by the system software.
Synchronize any program memory changes as required. (See Self-Modifying Code on page 172 for more
information about the instruction sequence necessary to synchronize changes to program memory
before executing the new instructions).
18. Start the system software.
System software is generally responsible for initializing and/or managing the rest of the MSR fields,
including:
a. MSR[FP] to enable or disable the execution of floating-point instructions
b. MSR[FE0,FE1] to enable/disable floating-point enabled exception type of program interrupts
c. MSR[PR] to specify user mode or supervisor mode
d. MSR[IS,DS] to specify application address space or system address space for instructions and data
System software can also enable and disable other threads through the CCR0, TENS, and TENC SPRs;
see Section 2.3.2 Thread Run State on page 71 for details on their usage.
Initialization
Page 168 of 864
Version 1.3
October 23, 2012