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User's Manual
A2 Processor
The an_ac_reset_x_complete inputs must be active for a minimum of one clock pulse to set the DBSR[MRR]
and TSR[WRS] reset status bits. If more than one reset input is active at the same time, they are set using the
following priority: highest = type 3, next = type 2, lowest = type 1.
4.3.2.1 Debug Facility Reset Status
The Most Recent Reset field of the Debug Status Register (DBSR[MRR]) indicates the type of reset that
occurred last. The flush 0 scan of the core's reset initializes this field to 0b00. Once initialized by the core
reset, chip level reset controls can use the an_an_reset_x_complete signals to provide additional reset status
to software. The DBSR[MRR] field of all threads is updated with the same reset status.
DBSR[MRR]:
• 0b00 - No reset status since last cleared.
• 0b01 - A type 1 reset has occurred.
• 0b10 - A type 2 reset has occurred.
• 0b11 - A type 3 reset has occurred.
4.3.2.2 Timer Facility Reset Status
The Watchdog Timer Reset Status field of the Timer Status Register (TSR[WRS]) indicates that a reset was
caused by a watchdog timer exception. The flush 0 scan of the core's reset initializes this field to 0b00. Once
initialized by the core reset, chip level reset controls can use the an_an_reset_x_complete signals to provide
additional reset status to software. The TSR[WRS] field of all threads is updated with the same reset status.
TSR[WRS]:
• 0b00 - No watchdog timer reset has occurred.
• 0b01 - The watchdog timer caused a type 1 reset.
• 0b10 - The watchdog timer caused a type 2 reset.
• 0b11 - The watchdog timer caused a type 3 reset.
Initialization
Page 162 of 864
Version 1.3
October 23, 2012
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