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User's Manual
A2 Processor
6.16.2 Indirect TLB Entry Page and Sub-Page Sizes
Each indirect TLB entry represents a hardware page table in memory, and there can be many disjoint page
tables existing in various areas of real memory. Each indirect entry has an associated page size (the size of
the virtual address area covered by this indirect entry, or the entry TSIZE field) and a sub-page size (denoting
smaller, same-sized "chunks" of the parent indirect entry page size). This processor supports two combina-
tions of page and sub-page sizes: 1 MB page size with 4 KB sub-page sizes, and 256 MB page size with
64 KB sub-page sizes. These combinations are indicated by the read-only EPTCFG register.
The overall size of each hardware page table is determined by the associated indirect entry page size and
sub-page size. Each of the page table entries (PTEs) of a particular hardware page table is 8 bytes (64 bits)
in length. For this processor, hardware page tables are either 2 KB bytes in length or 32 KB bytes in length.
This calculation is shown in Figure 6-5.
Figure 6-5. Indirect Entry to Page Table Size Calculation
Virtual Memory
Indirect Entry A
. . .
SIZE
= 1 MB
0
Indirect Entry B
. . .
SIZE
= 256 MB
1
The starting address of a given page table must be aligned to the page table's size. This virtual linear page
table placement with a given page size and sub-page size results in the page table's starting real address
LSB being determined by a certain bit of the indirect entry's RPN field. For the 1 MB/4 KB combination (a
2 KB page table size), the indirect entry RPN[52] is used as the LSB of the base real address of this page
table (that is, RA[53:60] is a given PTE's offset within that page table). For the 256 MB/64 KB combination (a
32 KB page table size), the indirect entry RPN[48] is used as the LSB of the base real address of this page
table (that is, RA[49:60] is a given PTE's offset within that page table). For this implementation, the indirect
entry RPN[53] is not required and is therefore treated as a reserved bit in both the TLB and MAS3.
Note: Even though each of the sub-page regions of a given indirect entry are represented by a backing PTE,
each PTE within a page table contains a variable page size field (see for the PTE format). This means that a
given PTE page size does not necessarily have to match the sub-page size of the indirect entry used to find
this PTE (that is, IND = 1 Entry[SPSIZE] does not necessarily equal PTE[Page Size]). For example, an oper-
ating system might choose to use 16 MB pages (a supported direct page size for this processor) in a particu-
Memory Management
Page 238 of 864
Sub-pages of
1 MB
SPSIZE
= 4 KB
0
4 KB
Each sub-page
256 entries 8 bytes/entry = 2 KB (page table A size)
region has an
associated PTE
Sub-pages of
256 MB
SPSIZE
= 64 KB
1
64 KB
Each sub-page
4 K entries 8 bytes/entry = 32 KB (page table B size)
region has an
associated PTE
= 256 entries in page table A
= 4 K entries in page table B
Version 1.3
October 23, 2012
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