Thread Priority; Program Priority Register (Ppr32) - IBM A2 User Manual

Bits Field Name
42:47 WC2
48:49 ///
50:55 WC1
56:57 ///
58:63 WC0

2.3.4 Thread Priority

Thread priority can be changed by writing the PPR32 register, executing an or Rx,Rx,Rx instruction, or by
causing an interrupt.

2.3.4.1 Program Priority Register (PPR32)

The program priority register controls thread priority. A2 hardware supports three physical priorities. In A2's
lowest hardware priority, the number of cycles between two instructions being issued is determined by
IUCR1[THRES]. See Instruction Unit Configuration Register 1 (IUCR1) on page 77.
The mapping of the three hardware priorities to the architected priorities in the PPR32 register is shown in
Table 2-3. An or Rx,Rx,Rx is used to set PPR32[PRI]; these are also shown in Table 2-3. Other defined or
Rx,Rx,Rx hints shown in Table 2-4 are ignored. PPR32[PRI] remains unchanged if the privilege state of the
processor executing the instruction is lower than the privilege indicated in Table 2-3. PPR32[PRI] also
remains unchanged if "000" is written to the field.
If MSR[EE] is 0 and PPR32 = low then thread priority is increased to medium; PPR32 is unchanged. When
MSR[EE] is 1, thread priority is determined by PPR32[PRI]. This function is provided to reduce delay in the
processing of interrupts.
Version 1.3
October 23, 2012
Initial
Value
0xF Thread 2 Wake Control
(0) 1 Disables sleep on waitrsv.
(1) 1 Disables sleep on waitimpl.
(2) 1 Enables wake on critical input, watchdog, critical doorbell, guest critical doorbell,
or guest machine check doorbell interrupts.
(3) 1 Enables wake on external input, performance monitor, doorbell, or guest doorbell
interrupts.
(4) 1 Enables wake on decrementer or user decrementer interrupts.
(5) 1 Enables wake on fixed interval timer interrupts.
0b00 Reserved
0xF Thread 1 Wake Control
(0) 1 Disables sleep on waitrsv.
(1) 1 Disables sleep on waitimpl.
(2) 1 Enables wake on critical input, watchdog, critical doorbell, guest critical doorbell,
or guest machine check doorbell interrupts.
(3) 1 Enables wake on external input, performance monitor, doorbell, or guest doorbell
interrupts.
(4) 1 Enables wake on decrementer or user decrementer interrupts.
(5) 1 Enables wake on fixed interval timer interrupts.
0b00 Reserved
0xF Thread 0 Wake Control
(0) 1 Disables sleep on waitrsv.
(1) 1 Disables sleep on waitimpl.
(2) 1 Enables wake on critical input, watchdog, critical doorbell, guest critical doorbell,
or guest machine check doorbell interrupts.
(3) 1 Enables wake on external input, performance monitor, doorbell, or guest doorbell
interrupts.
(4) 1 Enables wake on decrementer or user decrementer interrupts.
(5) 1 Enables wake on fixed interval timer interrupts.
Description
CPU Programming Model
User's Manual
A2 Processor
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